公开(公告)号：US20060071922A1

公开(公告)日：2006-04-06

申请号：US11242008

申请日：2005-10-04

Applicant: Yu-Pin Chou

Inventor： Yu-Pin Chou

IPC: G09G5/00

CPC classification number: G09G5/005 ,  G09G5/008

Abstract: A method for up/down converting display data employs steps of generating a first clock signal, generating display data, writing the display data into a buffer using the first clock signal, generating a second clock signal, reading out the display data written into the buffer using the second signal, and transmitting the read-out display data to a display module.

Abstract translation: 用于上/下转换显示数据的方法采用产生第一时钟信号，产生显示数据，使用第一时钟信号将显示数据写入缓冲器的步骤，产生第二时钟信号，读出写入缓冲器的显示数据 使用第二信号，并将读出的显示数据发送到显示模块。

公开(公告)号：US20060012438A1

公开(公告)日：2006-01-19

申请号：US11160767

申请日：2005-07-07

Applicant: Yu-Pin Chou ,  Chia-Liang Chiang

Inventor： Yu-Pin Chou ,  Chia-Liang Chiang

IPC: H03L7/00

CPC classification number: H03L7/0891 ,  H03L7/093

Abstract: A phase-locked loop includes a phase/frequency detector for generating phase error signal according to a reference signal and an input signal, a charge pump for outputting a voltage signal according to the phase error signal, a voltage-controlled oscillator for outputting an output signal corresponding to the phase error signal according to the voltage signal, an adaptive adjusting unit for outputting a control signal according to the phase error signal, so as to form a nonlinear between the output signal and the phase error signal.

Abstract translation: 锁相环包括用于根据参考信号和输入信号产生相位误差信号的相位/频率检测器，用于根据相位误差信号输出电压信号的电荷泵，用于输出输出的电压控制振荡器 根据电压信号对应于相位误差信号的信号，自适应调整单元，用于根据相位误差信号输出控制信号，以便在输出信号和相位误差信号之间形成非线性。

公开(公告)号：US20050001656A1

公开(公告)日：2005-01-06

申请号：US10609535

申请日：2003-07-01

Applicant: Yu-Pin Chou

Inventor： Yu-Pin Chou

IPC: H03D13/00

CPC classification number: H03D13/003

Abstract: A digital fractional phase detector is shown that uses a phase error detector for generating a phase error signal based on the phase difference between a reference clock signal and a feedback clock signal. A quantizer directly measures the pulse width of a phase error signal and outputs the value in a digital form. By directly measuring the phase error signal, quantization accuracy is increased. In order to calibrate the digital fractional phase detector, a calibration pulse generator generates a calibration pulse of a known duration and passes it to the quantizer.

Abstract translation: 示出了一种数字分数相位检测器，其使用相位误差检测器基于参考时钟信号和反馈时钟信号之间的相位差产生相位误差信号。 量化器直接测量相位误差信号的脉冲宽度，并以数字形式输出该值。 通过直接测量相位误差信号，量化精度提高。 为了校准数字分数相位检测器，校准脉冲发生器产生已知持续时间的校准脉冲并将其传递给量化器。

公开(公告)号：US08471859B2

公开(公告)日：2013-06-25

申请号：US12692389

申请日：2010-01-22

Applicant: Chia-Lung Hung ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

Inventor： Chia-Lung Hung ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

IPC: G09G5/39 ,  G09G5/36 ,  G06F12/02 ,  H04N7/01

CPC classification number: H04N7/0105 ,  H04N7/0132

Abstract: A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.

Abstract translation: 用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。 输入像素时钟不等于输出像素时钟。 帧写入控制器根据输入DE和输出DE生成写许可信号。 缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。 缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

公开(公告)号：US08284871B2

公开(公告)日：2012-10-09

申请号：US12501959

申请日：2009-07-13

Applicant: Tzuo-Bo Lin ,  Bing-Juo Chuang ,  Yu-Pin Chou

Inventor： Tzuo-Bo Lin ,  Bing-Juo Chuang ,  Yu-Pin Chou

IPC: H04L27/22

CPC classification number: H04L7/10 ,  G09G5/006 ,  G09G5/008 ,  G09G2370/12 ,  H04L7/046 ,  H04L25/4908

Abstract: A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed.

Abstract translation: 接收机包括 恢复电路，用于接收输入信号，并产生数据信号和恢复时钟; 处理电路，用于处理数据信号以产生处理的信号; 以及同步确定电路，用于根据处理的信号和第一参考值确定恢复时钟的同步状态。 数据信号包括同步模式，第一参考值对应于由处理电路处理的同步模式中的值的至少一部分。 还公开了接收机的方法。

公开(公告)号：US08212938B2

公开(公告)日：2012-07-03

申请号：US11822392

申请日：2007-07-05

Applicant: Jui-Yuan Tsai ,  Szu-Ping Chen ,  Yu-Pin Chou

Inventor： Jui-Yuan Tsai ,  Szu-Ping Chen ,  Yu-Pin Chou

IPC: H04N9/72

CPC classification number: H04N5/08 ,  H04N5/185 ,  H04N9/44

Abstract: A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.

Abstract translation: 公开了一种同步信号采集装置，其包括晶体管，电阻器，钳位器，模拟多路复用器和比较器。 当在复合HS模式下操作时，在产生同步信号HS之前，本发明使用常规电路在启动时提取复合同步信号，从而允许相关电路产生同步信号HS和钳位信号。 然后，使用模式选择信号来禁用自动钳位模式并将模拟多路复用器切换到强制钳位模式。 此时，阻尼器的输出电压由使用者而不是过程设定; 因此，直流电压电平更可控，但由于过程变化或温度变化而不会发生漂移。

公开(公告)号：US07893997B2

公开(公告)日：2011-02-22

申请号：US11273885

申请日：2005-11-15

Applicant: Yu Pin Chou

Inventor： Yu Pin Chou

IPC: H04N7/01 ,  H04N11/20 ,  H04N5/08 ,  H04N9/74 ,  H04N3/14 ,  H03L7/00 ,  G09G5/02

CPC classification number: G09G5/008 ,  H03L7/0991 ,  H03L7/18

Abstract: A method for generating a video clock and an associated target image frame is disclosed. The method generates an output clock signal for outputting a target image frame to a panel according to a frame pixel number and a vertical synchronization signal (Vsync). The target image frame corresponds to a source image frame. The frame pixel number is the number of total pixels included in a predetermined frame format, and the Vsync signal is an input Vsync signal or an output Vsync signal. The period of the output clock signal is the result of the period of the Vsync divided by the frame pixel number. In this manner, the format of the target image frame can remain substantially fixed, and is substantially equal to the predetermined frame format.

Abstract translation: 公开了一种用于产生视频时钟和相关联的目标图像帧的方法。 该方法根据帧像素数和垂直同步信号（Vsync）产生用于将目标图像帧输出到面板的输出时钟信号。 目标图像帧对应于源图像帧。 帧像素数是包括在预定帧格式中的总像素数，Vsync信号是输入Vsync信号或输出Vsync信号。 输出时钟信号的周期是Vsync的周期除以帧像素数的结果。 以这种方式，目标图像帧的格式可以保持基本上固定，并且基本上等于预定的帧格式。

公开(公告)号：US07778321B2

公开(公告)日：2010-08-17

申请号：US11165029

申请日：2005-06-24

Applicant: Yu-Pin Chou ,  Chao-Hsin Lu

Inventor： Yu-Pin Chou ,  Chao-Hsin Lu

IPC: H03K5/159

CPC classification number: H04L25/03019 ,  H04L2025/03764

Abstract: A method for adjusting parameters of an adaptive equalizer makes use of a transmitted signal received by a receiving end to adjust parameters of an adaptive equalizer. First, signal strengths of a first frequency band and a second frequency band in the transmitted signal are detected. The signal strengths of the first frequency band and the second frequency band are then compared to get a compensation ratio, i.e., the total compensation quantity of the first frequency band to the second frequency band. Finally, the parameter setting of the equalizer is adjusted according to feedback of the compensation ratio. Optimum gain control of the adaptive equalizer can thus be accomplished to compensate signal attenuation to the transmitted signal caused by the channel.

Abstract translation: 用于调整自适应均衡器的参数的方法利用由接收端接收到的发送信号来调整自适应均衡器的参数。 首先，检测发送信号中的第一频带和第二频带的信号强度。 然后比较第一频带和第二频带的信号强度以获得补偿比，即第一频带的总补偿量到第二频带。 最后，根据补偿比的反馈调整均衡器的参数设置。 因此，可以实现自适应均衡器的最佳增益控制，以补偿由信道引起的对发射信号的信号衰减。

公开(公告)号：US20090153574A1

公开(公告)日：2009-06-18

申请号：US12275912

申请日：2008-11-21

Applicant: Yu-Pin Chou ,  Tzou-Bo Lin ,  Chih-Ming Lee ,  Ming-Syun Wu

Inventor： Yu-Pin Chou ,  Tzou-Bo Lin ,  Chih-Ming Lee ,  Ming-Syun Wu

IPC: G09G5/39

CPC classification number: G09G5/003 ,  G09G5/006 ,  G09G2370/047

Abstract: A system for updating firmware through a DisplayPort interface includes a source device with a DisplayPort interface, and a sink device with a DisplayPort interface. The source device includes a storage circuit for storing and providing an updated firmware, and a source device auxiliary channel for outputting the updated firmware with an auxiliary channel signal format. The sink device includes a sink device auxiliary channel for receiving the updated firmware with the auxiliary channel signal format and thereby generating an output signal, an I2C auxiliary channel device servicer for receiving the output signal and generating an I2C protocol updated firmware, and a memory unit for updating firmware according to the I2C protocol updated firmware. A method for updating firmware is also disclosed.

Abstract translation: 通过DisplayPort接口更新固件的系统包括具有DisplayPort接口的源设备和具有DisplayPort接口的接收器设备。 源设备包括用于存储和提供更新的固件的存储电路，以及用于以辅助信道信号格式输出更新的固件的源设备辅助通道。 宿设备包括宿设备辅助通道，用于以辅助通道信号格式接收更新的固件，从而生成输出信号，用于接收输出信号并产生I2C协议更新固件的I2C辅助通道设备服务器，以及存储器单元 根据I2C协议更新固件更新固件。 还公开了一种用于更新固件的方法。

公开(公告)号：US20090153545A1

公开(公告)日：2009-06-18

申请号：US12314601

申请日：2008-12-12

Applicant: Yu-Pin Chou ,  Tzuo-Bo Lin ,  Ming-Syun Wu

Inventor： Yu-Pin Chou ,  Tzuo-Bo Lin ,  Ming-Syun Wu

IPC: G09G5/00

CPC classification number: G09G5/006 ,  G09G5/005 ,  G09G2370/12

Abstract: A timing controller for a display processing device includes: a plurality of predetermined pins for receiving an image signal by a pin-share method, wherein the image signal is a first format image signal or a second format image signal; a detector coupled to the predetermined pins and for detecting at least one of the predetermined pins to determine whether the image signal is the first format image signal or the second format image signal and outputting a detection result; and a processor coupled to the detector and for processing the image signal according to the detection result to generate and output a timing control signal.

Abstract translation: 一种用于显示处理装置的定时控制器包括：多个预定引脚，用于通过引脚分配方式接收图像信号，其中图像信号是第一格式图像信号或第二格式图像信号; 检测器，其耦合到所述预定引脚并且用于检测所述预定引脚中的至少一个以确定所述图像信号是所述第一格式图像信号还是所述第二格式图像信号，并输出检测结果; 以及耦合到所述检测器并用于根据所述检测结果来处理所述图像信号的处理器以产生和输出定时控制信号的处理器。