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    Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement
    56.
    发明授权
    Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement 有权
    通过增加掺杂剂约束，包括高k金属栅极堆叠的PFET晶体管的性能增强

    公开(公告)号：US08404550B2

    公开(公告)日：2013-03-26

    申请号：US12905383

    申请日：2010-10-15

    申请人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

    发明人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66651

    摘要： In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.

    摘要翻译： 在包含高k金属栅电极结构的P沟道晶体管中，至少在阈值调节半导体材料（例如硅/锗材料）中可以通过掺入扩散阻挡物质获得优异的掺杂剂分布，例如 在形成阈值调节半导体材料之前。 因此，漏极和源极延伸区域可以被提供有高的掺杂剂浓度，以获得目标米勒电容，而不会导致低于阈值调节半导体材料的不适当的掺杂剂扩散，否则可能导致增加的漏电流和增加的穿孔风险 事件

    Multiple gate transistor having fins with a length defined by the gate electrode
    57.
    发明授权
    Multiple gate transistor having fins with a length defined by the gate electrode 有权
    多栅极晶体管具有由栅电极限定的长度的散热片

    公开(公告)号：US08183101B2

    公开(公告)日：2012-05-22

    申请号：US12620265

    申请日：2009-11-17

    申请人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Andrew Waite

    发明人： Robert Mulfinger ,  Andy Wei ,  Jan Hoentschel ,  Andrew Waite

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66795 ,  H01L29/785

    摘要： The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.

    摘要翻译： 多栅极晶体管的漏极和源极区可以通过使用用于形成漏极和源极掺杂物分布的占位符结构而形成，而不需要外延生长工艺，随后掩蔽漏极和源极区域并去除占位符结构以露出​​沟道 晶体管的面积。 此后，可以对相应的翅片进行构图，并且可以形成栅电极结构。 因此，由于避免了外延生长过程，可以实现缩短的循环时间。

    STRAIN TRANSFORMATION IN BIAXIALLY STRAINED SOI SUBSTRATES FOR PERFORMANCE ENHANCEMENT OF P-CHANNEL AND N-CHANNEL TRANSISTORS
    59.
    发明申请
    STRAIN TRANSFORMATION IN BIAXIALLY STRAINED SOI SUBSTRATES FOR PERFORMANCE ENHANCEMENT OF P-CHANNEL AND N-CHANNEL TRANSISTORS 有权
    用于双通道和N沟道晶体管性能增强的双向应变SOI衬底中的应变变换

    公开(公告)号：US20100301416A1

    公开(公告)日：2010-12-02

    申请号：US12784819

    申请日：2010-05-21

    申请人： Jan Hoentschel ,  Stefan Flachowsky ,  Andy Wei

    发明人： Jan Hoentschel ,  Stefan Flachowsky ,  Andy Wei

    IPC分类号： H01L27/12 ,  H01L21/782

    CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7846

    摘要： In advanced SOI devices, a high tensile strain component may be achieved on the basis of a globally strained semiconductor layer, while at the same time a certain compressive strain may be induced in P-channel transistors by appropriately selecting a height-to-length aspect ratio of the corresponding active regions. It has been recognized that the finally obtained strain distribution in the active regions is strongly dependent on the aspect ratio of the active regions. Thus, by selecting a moderately low height-to-length aspect ratio for N-channel transistors, a significant fraction of the initial tensile strain component may be preserved. On the other hand, a moderately high height-to-length aspect ratio for the P-channel transistor may result in a compressive strain component in a central surface region of the active region.

    摘要翻译： 在先进的SOI器件中，可以在全局应变半导体层的基础上实现高拉伸应变分量，同时通过适当地选择高度 - 长度方面，可以在P沟道晶体管中产生一定的压缩应变 相应活性区的比例。 已经认识到，有效区域中最终获得的应变分布强烈地取决于有源区的纵横比。 因此，通过为N沟道晶体管选择中等的高度 - 长度长宽比，可以保留初始拉伸应变分量的很大一部分。 另一方面，用于P沟道晶体管的中等高度的长宽比可能导致有源区的中心表面区域中的压缩应变分量。