公开(公告)号：US09766857B2

公开(公告)日：2017-09-19

申请号：US14582836

申请日：2014-12-24

Applicant: ARM Limited

Inventor： David Raymond Lutz ,  Neil Burgess ,  Christopher Neal Hinds

IPC: G06F7/48 ,  G06F7/483 ,  G06F7/499 ,  G06F9/30 ,  G06F17/16 ,  H03M7/12 ,  H03M7/24 ,  G06F11/34 ,  G06F11/36 ,  G06F5/01 ,  G06F7/38 ,  G06F7/507 ,  G06F9/38 ,  G06F7/506

CPC classification number: G06F7/483 ,  G06F5/012 ,  G06F7/38 ,  G06F7/48 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/49921 ,  G06F7/49942 ,  G06F7/506 ,  G06F7/507 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/3885 ,  G06F11/3404 ,  G06F11/3476 ,  G06F11/348 ,  G06F11/3636 ,  G06F11/3644 ,  G06F11/3648 ,  G06F17/16 ,  G06F2201/865 ,  G06F2207/483 ,  H03M7/12 ,  H03M7/24

Abstract: An apparatus includes processing circuitry to perform one or more arithmetic operations for generating a result value based on at least one operand. For at least one arithmetic operation, the processing circuitry is responsive to programmable significance data indicative of a target significance for the result value, to generate the result value having the target significance. For example, this allows programmers to set a significance boundary for the arithmetic operation so that it is not necessary for the processing circuitry to calculate bit values having a significance outside the specified boundary, enabling a performance improvement.

公开(公告)号：US09720646B2

公开(公告)日：2017-08-01

申请号：US14939175

申请日：2015-11-12

Applicant: ARM LIMITED

Inventor： Neil Burgess ,  David Raymond Lutz ,  Christopher Neal Hinds

IPC: G06F5/01 ,  G06F7/483 ,  G06F7/509 ,  G06F7/499

CPC classification number: G06F5/012 ,  G06F7/483 ,  G06F7/49947 ,  G06F7/50 ,  G06F7/5095 ,  G06F2207/4924

Abstract: A redundant representation is provided where an M-bit value represents a P-bit numeric value using a plurality of N-bit portions, where M>P>N. An anchor value identifies the significance of bits of each N-bit, and within a group of at least two adjacent N-bit portions, two or more overlap bits of a lower N-bit portion of the group have a same significance as two or more least significant bits of at least one upper N-bit portion of the group. A plurality of operation circuit units can perform a plurality of independent N-bit operation in parallel, each N-bit operation comprising computing a function of corresponding N-bit portions of at least two M-bit operand values having the redundant representation to generate a corresponding N-bit portion of an M-bit result value having the redundant representation. This enables fast associative processing of relatively long M-bit values in the time taken for performing an N-bit operation.

公开(公告)号：US09678715B2

公开(公告)日：2017-06-13

申请号：US14528326

申请日：2014-10-30

Applicant: ARM LIMITED

Inventor： Neil Burgess ,  David Raymond Lutz

IPC: G06F7/50 ,  G06F17/16 ,  G06F7/02 ,  G06F7/544 ,  G06F7/57 ,  G06F9/30 ,  G06F7/509

CPC classification number: G06F7/50 ,  G06F7/02 ,  G06F7/509 ,  G06F7/544 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30036 ,  G06F17/16

Abstract: An apparatus 8 for performing a selectable one of multi-element comparison and multi-element addition is formed from a carry propagate adders stage 12 supplied with four non-final intermediate operands formed from the input vector, a non-final limit value selecting stage 14, which when performing a multi-element comparison serves to select, in dependence upon at least carry save values generated by the carry propagate adder, limit values that are of a larger or a smaller value of a pair of elements. A final intermediate operand forming stage 16 forms final intermediate operands from two non-final intermediate sum values from the carry propagate adders stage 12 and supplies these to a final output adder stage 18 which forms a sum of these two final intermediate operands to generate an output operand which can be either one or more candidates for limit values that will be a maximum or minimum value, or a sum value, or partial sum values in the case of a multi-element addition.

公开(公告)号：US09658827B2

公开(公告)日：2017-05-23

申请号：US14519787

申请日：2014-10-21

Applicant: ARM LIMITED

Inventor： David Raymond Lutz ,  Neil Burgess

IPC: G06F7/483 ,  G06F7/485 ,  G06F7/535 ,  G06F7/552 ,  G06F7/57

CPC classification number: G06F7/485 ,  G06F7/483 ,  G06F7/535 ,  G06F7/5525 ,  G06F7/57 ,  G06F2207/48 ,  G06F2207/5356

Abstract: A data processing apparatus has floating-point add circuitry for performing a floating-point add operation for adding or subtracting two floating-point operands. The apparatus also has reciprocal estimation circuitry for performing a reciprocal estimation operation on a first operand to generate a reciprocal estimate value which represents an estimate of a reciprocal of a first operand or an estimate or a reciprocal of the square root of the first operand. The reciprocal estimation circuitry is physically distinct from the floating-point adder circuitry, which allows both the reciprocal estimate and the add operations to be faster.

公开(公告)号：US09608662B2

公开(公告)日：2017-03-28

申请号：US14498118

申请日：2014-09-26

Applicant: ARM Limited

Inventor： David Raymond Lutz ,  Neil Burgess

IPC: G06F5/01 ,  H03M7/24

CPC classification number: H03M7/24

Abstract: A data processing apparatus has floating-point add circuitry to perform a floating-point addition operation for adding or subtracting two floating-point values. The apparatus also has conversion circuitry to perform a conversion operation to convert a first floating-point value into a second value having a different format. The conversion circuitry is capable of converting to an integer or fixed-point value. The conversion circuitry is physically distinct from the floating-point add circuitry.