公开(公告)号：US10269416B1

公开(公告)日：2019-04-23

申请号：US15789715

申请日：2017-10-20

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra

IPC: G11C11/417 ,  G11C11/418 ,  H01L23/528 ,  H01L27/11 ,  G11C11/412

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to multiple dummy wordline loads via a dummy wordline. The integrated circuit may include demultiplexer circuitry coupled to a first path of the dummy wordline between the dummy wordline driver and the multiple dummy wordline loads. The integrated circuit may include multiplexer circuitry coupled to a second path of the dummy wordline between the multiple dummy wordline loads and a dummy bitline load. The demultiplexer circuitry and the multiplexer circuitry may be controlled with one or more selection signals to select at least one of the multiple dummy wordline loads.

公开(公告)号：US10217496B1

公开(公告)日：2019-02-26

申请号：US15907951

申请日：2018-02-28

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Satinderjit Singh ,  Shri Sagar Dwivedi ,  Bo Zheng ,  Fakhruddin Ali Bohra

IPC: G11C7/00 ,  G11C7/12 ,  G11C7/10 ,  G11C11/4097 ,  G11C11/419

Abstract: Various implementations described herein are directed to an integrated circuit with memory circuitry having an array of bitcells that are accessible via multiple bitlines. The integrated circuit may include a write driver coupled to at least one bitline of the multiple bitlines through a column multiplexer. The integrated circuit may include a pass transistor coupled to the write driver and the column multiplexer via a write data line. The integrated circuit may include a charge storage device coupled between the pass transistor and write assist enable circuitry. The integrated circuit may include a transmission gate coupled to a gate of the write driver. The integrated circuit may include a clamp transistor coupled between the gate of write driver and the charge storage device such that the clamp transistor receives a voltage assist signal from the charge storage device at the gate of the write driver.

公开(公告)号：US20170194046A1

公开(公告)日：2017-07-06

申请号：US14986215

申请日：2015-12-31

Applicant: ARM Limited

Inventor： Gus Yeung, JR. ,  Fakhruddin Ali Bohra ,  George Lattimore

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C8/16 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419 ,  G11C2207/2209

Abstract: Various implementations described herein may refer to and may be directed to using port modes with memory. In one implementation, a memory device may include access control circuitry used to selectively activate one of a plurality of first word-lines based on first address signals from a first access port, and used to selectively activate one of a plurality of second word-lines based on assigned address signals. The access control circuitry may include address selection circuitry configured to select the assigned address signals based on a port mode signal, where the address selection circuitry selects the first address signals as the assigned address signals when the port mode signal indicates a single port mode, and where the address selection circuitry selects second address signals from a second access port as the assigned address signals when the port mode signal indicates a dual port mode.

公开(公告)号：US20170178700A1

公开(公告)日：2017-06-22

申请号：US15451089

申请日：2017-03-06

Applicant: ARM Limited ,  The Regents of the University of Michigan

Inventor： Mahmood Khayatzadeh ,  Massimo Bruno Alioto ,  David Theodore Blaauw ,  Dennis Michael Chen Sylvester ,  Fakhruddin Ali Bohra

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/065 ,  G11C5/063 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/18 ,  G11C8/16 ,  G11C11/419 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/002 ,  G11C2207/005

Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.