摘要:
A data driven type information processor includes a data driven type information processing unit, and a download unit. The information processing unit includes a program storing unit and an input/output control unit of a data packet for storing information stored in a data packet including a load instruction into the program storing unit and for carrying out a data driven type process on data packets including other instructions according to information stored in the program storing unit. The download unit downloads program data to the information processing unit by applying a data packet including the load instruction and program data to be stored in the program storing unit. The download unit includes a memory for storing program data, a readout circuit for reading out a set of program data stored in the memory, and a packet generation circuit for generating a data packet including the load instruction and readout program data to provide the same to the input/output control unit of the information processing unit. The memory may store a plurality of sets of program data.
摘要:
A memory interface apparatus includes: a pipeline register holding a data packet from a transmission path to provide an instruction code, a generation number, and data separately; a memory access unit accessing an image memory according to the instruction code, a circuit latching the output of the image memory; an ALU carrying out an operation specified by the instruction code from the pipeline register between data from the pipeline register and the output of the latch circuit for output of the operation result; a selector responsive to a select signal for selecting one of data from the pipeline register and the output of the ALU to apply the selected result to the image memory as data; an output unit generating a data packet including a result of a series of complex operation carried out by the pipeline register, the image memory, and the ALU for output; a transmission control unit controlling transmission of a data packet on the transmission path carried out by the pipeline register and the output unit; and a control unit responsive to the instruction code from the pipeline register for controlling the ALU, the memory access unit, the image memory, the latch circuit, the selector, the output unit, and the transmission control unit so that a series of complex operation processing including an access to the image memory specified by the instruction code is carried out.
摘要:
A conveyor mechanism for transferring cylindrical articles, such as, cigarettes embodies a single belt conveyor which does the conveying from a lower level to a higher level. The surface used for conveyance has a curved portion unlike belt conveyors in general use and a plurality of pins project from at least one side of the belt in parallel relation to each other. At the curved section, these pins are held by a suitable means such that the belt maintains the curvature. Cigarettes or other cylindrical objects are fed by the internal surface of the curving belt and an auxiliary belt conveyor.
摘要:
A method of producing a yoke of a rotary electric machine wherein a cylindrical blank is formed comprises extrusion forming a semi-finished article having abutting surfaces at axial opposite ends in the first step. The abutting surfaces are subjected to coining in the second step whereby the two abutting surfaces can have a spacing interval of high accuracy and can be disposed parallel to each other.
摘要:
A self-synchronous FIFO memory device (100) has a structure in which n self-synchronous data transmission lines (111-11n) are arrayed in parallel. An input control section (101) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a first transfer request signal, a first acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a preceding-stage section. Further, an output control section (102) selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a second transfer request signal, a second acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a succeeding-stage section.
摘要:
A data transmission line used connected continuously in a plurality of stages in an asynchronous system includes a transfer control circuit, synchronous and asynchronous data holding circuits and a timing adjustment circuit. The data transmission line receives and holds data transmitted from a data transmission line of a preceding stage or data output from an external clock synchronous circuit, and outputs and transmits the data to a data transmission line of a succeeding stage. Timing adjustment circuit adjusts data input timing by the transfer control circuit to the synchronous and asynchronous data holding circuits so that data can surely be taken in. It becomes possible to surely take in and transmit data output from external synchronous system in an asynchronous data transmission line at a desired arbitrary timing.
摘要:
An input port receives input data X, generates input packets by adding generation numbers and node numbers indicative of prescribed destinations, in the order of reception, and in addition, generates a data packet from a separately input clock signal. The input data packet is written to an image memory using the generation number in the packet as an address signal, or read from the image memory using the generation number in the data packet as an address signal. Operation is performed in accordance with the input data packet or the data packet read from the image memory by a memory interface, and the processed data packet is output to the outside of a data driven engine, a memory interface or a data driven type processor.
摘要:
An image operation processing apparatus is connected to a memory. The apparatus processes, by accessing the memory, a data packet including instruction information and an address of a prescribed address space. The apparatus realizes an address translation process for translating the address included in an incoming data packet to an address of a partial address space smaller than the prescribed address space. It further realizes a memory access process for accessing the memory in accordance with the address translated by the address translation process. Finally, it performs a process in accordance with the instruction information included in the data packet.
摘要:
A data driven information processor capable of readily performing appropriate processing to input data according to their meanings includes a data packet forming portion forming a data packet having a tag including a generation number, a destination number, instruction information and a constant value based on externally input data. The data packet forming portion includes a generation number generation processing portion for generating a multi-dimensional generation number to be added to input data based on an order of the data and a destination number generation processing portion for generating a tag as a function of a generation number generated by the generation number generation processing portion. One of a generation number operation processing portion performing operation for each dimension of a generation number and a copy processing portion copying a portion of a generation number into a destination number, or both of these processing portions, may also be provided.
摘要:
Function processor FP of a data driven type information processor includes mechanism A receiving plural field generation number GN (representing pixel coordinate information), instruction code OPC, and condition X determining a divisional configuration of the generation number. Mechanism A takes out a bit field designated by instruction code OPC and/or the condition from applied generation number GN. Data of the taken out bit field is sent to arithmetic and logic unit A. Arithmetic and logic unit A carries out operation between data of the bit field and right data R-DATA. The operation result is sent to mechanism B. Mechanism B receives instruction code OPC, generation number GN, and condition X determining a divisional configuration of the generation number. The above described operation result is stored in the bit field of generation number GN designated by instruction code OPC and/or condition X.