摘要:
A gate structure is formed overlying a substrate. A source/drain region of the substrate is exposed to a soluction comprising ammonium hydroxide, hydrogen peroxide, and deionized water to etch an upper-most semiconductor porton of the source/drain region.
摘要:
A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.
摘要:
High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolytically plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, on a semiconductor substrate, typically a silicon-based substrate, and then reacting the precursor layer with oxygen or with oxygen and the semiconductor substrate to form the at least one refractory or lanthanum series transition metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.
摘要:
A method for depositing conductive material inside openings within an integrated circuit uses chemical solution deposition. The method includes applying the integrated circuit having the openings with a metalorganic decomposition precursor. The metalorganic decomposition precursor on the integrated circuit is pyrolyzed in a reducing ambient to form a layer of conductive material. For example, if the reducing ambient includes one of hydrogen gas, or a hydrogen and nitrogen gas mix, reactive hydrogen, or ultra high vacuum substantially devoid of oxygen, a conductive layer of metal forms from pyrolyzing the metalorganic decomposition precursor in such a reducing ambient. If the reducing ambient includes reactive nitrogen, a conductive layer of metal nitride forms from pyrolyzing the metalorganic decomposition precursor in such a reducing ambient. The present invention which uses metalorganic decomposition precursors which are chemical solutions with high wetability may be used to particular advantage for depositing a barrier layer and copper within small geometry openings for metal interconnects.
摘要:
A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.
摘要:
A process for, and apparatus for, Chemically-Mechanically Polishing (CMP) a semiconductor wafer with a slurry including ElectroRheological (ER) and/or MagnetoRheological (MR) fluids. The combination of the materials and an electric field provides inherent tuning of polishing rates, locally and globally, and improves flatness and uniformity, as well as minimizing recession and erosion.
摘要:
A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.
摘要:
Methods and systems for permitting thickness control of the selective epitaxial growth (SEG) layer in a semiconductor manufacturing process, for example raised source/drain applications in CMOS technologies, are presented. These methods and systems provide the capability to measure the thickness of an SEG film in-situ utilizing optical ellipsometry equipment during or after SEG layer growth, prior to removing the wafer from the SEG growth tool. Optical ellipsometry equipment can be integrated into the SEG platform and control software, thus providing automated process control (APC) capability for SEG thickness. The integration of the ellipsometry equipment may be varied, dependent upon the needs of the fabrication facility, e.g., integration to provide ellipsometer monitoring of a single process tool, or multiple tool monitoring, among other configurations.
摘要:
Monitoring of parameters using remote sensors, which are attached directly to the product material, allows for non-intrusive entry into the manufacturing area, via the same robotic handling or automated systems used to transport the standard product material. Data is recorded from the sensors, by wireless transmission, or when a signal is impassible, on-board memory will store the data for later downloading.