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    Reduced dopant deactivation of source/drain extensions using laser thermal annealing
    3.
    发明授权
    Reduced dopant deactivation of source/drain extensions using laser thermal annealing 有权
    使用激光热退火减少源/漏扩展的掺杂剂失活

    公开(公告)号：US06812106B1

    公开(公告)日：2004-11-02

    申请号：US10341366

    申请日：2003-01-14

    Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

    Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

    IPC: H01L21336

    CPC classification number: H01L21/28194 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606

    Abstract: Dopant deactivation of source/drain extensions during silicidation is reduced by forming deep source/drain regions using a disposable dummy gate as a mask, forming metal silicide layers on the deep source/drain regions, removing the dummy gate and then forming the source/drain extensions using laser thermal annealing. Embodiments include angular ion implantation, after removing the dummy gate, to form spaced apart pre-amorphized regions, ion implanting to form source/drain extension implants extending deeper into the substrate than the pre-amorphized regions, and then laser thermal annealing to activate the source/drain extensions having a higher impurity concentration at the main surface of the substrate than deeper into the substrate. Subsequent processing includes forming sidewall spacers, a gate dielectric layer and then the gate electrode.

    Abstract translation: 通过使用一次性虚拟栅极作为掩模形成深源极/漏极区域，在深度源极/漏极区域形成金属硅化物层，去除虚拟栅极，然后形成源极/漏极 扩展使用激光热退火。 实施例包括角度离子注入，在去除虚拟栅极之后，形成间隔开的非晶化区域，离子注入以形成比预非晶化区域更深地延伸到衬底中的源极/漏极延伸植入物，然后激光热退火以激活 源/漏扩展在衬底的主表面具有较高的杂质浓度，而不是深入衬底。 随后的处理包括形成侧壁间隔物，栅介质层，然后形成栅电极。

    Formation of deep amorphous region to separate junction from end-of-range defects
    5.
    发明授权
    Formation of deep amorphous region to separate junction from end-of-range defects 有权
    形成深非晶区域以将结点与端范围缺陷分离

    公开(公告)号：US06680250B1

    公开(公告)日：2004-01-20

    申请号：US10145740

    申请日：2002-05-16

    Applicant: Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

    Inventor： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

    IPC: H01L2144

    CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268

    Abstract: A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate. Inert dopants are then implanted within the substrate to form amorphized source/drain regions in the substrate extending to a first depth significantly greater than the intended junction depth. The amorphized source/drain regions are implanted with source/drain dopants such that the dopants extend into the substrate to a second depth less than the first depth, above and spaced apart from the end-of-range defect region created at the first depth by the amorphization process. Laser thermal annealing recrystallizes the amorphous regions, activates the source/drain regions and forms source/drain junctions. Because the recrystallization front velocity towards the substrate main surface is greater than the dopant atom velocity in the liquid substrate during laser thermal annealing, the junctions are not pushed down to the amorphous/crystalline silicon interface. Thus, end-of-range defects are located in a region below and spaced apart from the junctions, and the defects are not located in the activated source/drain regions. Junction leakage as a result of the end-of-range defects is thereby reduced.

    Abstract translation: 一种制造MOSFET半导体器件的方法包括：在栅极电极和衬底之间在衬底上形成栅极电极和栅极氧化物。 然后将惰性掺杂剂注入衬底内以在衬底中形成非晶化的源极/漏极区域，延伸到明显大于预期结点深度的第一深度。 非晶化源极/漏极区域注入源极/漏极掺杂剂，使得掺杂剂延伸到衬底中的第二深度小于第一深度的第二深度，在第一深度之上，并且与在第一深度处产生的端部范围缺陷区域间隔开 非晶化过程。 激光热退火使非晶区再结晶，激活源极/漏极区并形成源极/漏极结。 因为朝向衬底主表面的再结晶前向速度大于激光热退火期间液体衬底中的掺杂剂原子速度，所以接合点不被推到非晶/硅晶界面。 因此，距离范围缺陷位于与接合点下方和间隔开的区域中，并且缺陷不位于活化的源极/漏极区域中。 因此，由于距离范围缺陷导致的结漏电减少。

    Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors
    6.
    发明授权
    Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors 有权
    用于嵌入栅极MOS晶体管的介电材料前体材料的无电沉积

    公开(公告)号：US06559051B1

    公开(公告)日：2003-05-06

    申请号：US09679881

    申请日：2000-10-05

    Applicant: Matthew S. Buynoski ,  Paul R. Besser ,  Paul L. King ,  Eric N. Paton ,  Qi Xang

    Inventor： Matthew S. Buynoski ,  Paul R. Besser ,  Paul L. King ,  Eric N. Paton ,  Qi Xang

    IPC: H01L2144

    CPC classification number: H01L21/28194 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66583

    Abstract: High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, such as of Zr and/or Hf, on a silicon-based semiconductor substrate and then reacting the precursor layer with oxygen or with oxygen and the Si-based semiconductor substrate to form the at least one metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.

    Abstract translation: 通过无电镀法形成高质量电介质层，例如由至少一种耐火材料或镧系列过渡金属氧化物或硅酸盐构成的高k电介质层，用作叠层金属栅极MOS晶体管和CMOS器件中的栅极绝缘体层 金属或金属基电介质前体层，其在硅基半导体衬底上包含至少一种难熔或镧系过渡金属，例如Zr和/或Hf，然后使前体层与氧或氧与Si反应 的半导体衬底以形成至少一种金属氧化物或硅酸盐。 本发明的方法在至少形成栅极绝缘体层的初始阶段期间防止或至少基本上减少氧接触到衬底表面，从而最小化半导体衬底/栅极处的氧诱导表面状态的有害形成 绝缘子接口。

    Scanning laser thermal annealing
    7.
    发明授权
    Scanning laser thermal annealing 有权
    扫描激光热退火

    公开(公告)号：US07351638B1

    公开(公告)日：2008-04-01

    申请号：US10021782

    申请日：2001-12-18

    Applicant: Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

    Inventor： Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

    IPC: H01L21/336

    CPC classification number: H01L21/268 ,  H01L21/26513 ,  H01L29/6659

    Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, implanting dopants into the substrate and activating the dopants using laser thermal annealing. During annealing, the laser and substrate are moved relative to one another, and the movement of the laser and the substrate relative to one another does not pause between and during activating one portion of the source/drain regions and activating another portion of the source/drain regions. Each pulse from the laser can respectively irradiate different portions of the source/drain regions, and a spot area of the laser is less than 50 millimeter2.

    Abstract translation: 一种制造半导体器件的方法包括在衬底上形成栅电极，将掺杂剂注入到衬底中并使用激光热退火激活掺杂剂。 在退火期间，激光器和衬底相对于彼此移动，并且激光器和衬底相对于彼此的运动在激活源极/漏极区域的一部分之间和在激活源极/漏极区域的另一部分之间不间断， 漏区。 来自激光器的每个脉冲可以分别照射源极/漏极区域的不同部分，并且激光器的斑点面积小于50毫米2。

    Front side seal to prevent germanium outgassing
    8.
    发明授权
    Front side seal to prevent germanium outgassing 失效
    前侧密封防止锗脱气

    公开(公告)号：US06921709B1

    公开(公告)日：2005-07-26

    申请号：US10620194

    申请日：2003-07-15

    Applicant: Eric N. Paton ,  Haihong Wang ,  Qi Xiang

    Inventor： Eric N. Paton ,  Haihong Wang ,  Qi Xiang

    IPC: H01L21/265 ,  H01L21/336 ,  H01L21/84 ,  H01L29/10

    CPC classification number: H01L21/84 ,  H01L21/2652 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7842 ,  Y10S438/923 ,  Y10S438/933

    Abstract: A method of manufacturing an integrated circuit having a gate structure above a substrate that includes germanium utilizes at least one layer as a seal. The layer advantageously can prevent back sputtering and outdiffusion. A transistor can be formed in the substrate by doping through the layer. Another layer can be provided below the first layer. Layers of silicon dioxide, silicon carbide, silicon nitride, titanium, titanium nitride, titanium/titanium nitride, tantalum nitride, and silicon carbide can be used.

    Abstract translation: 制造具有在包括锗的衬底之上的栅极结构的集成电路的方法利用至少一层作为密封。 该层有利地可以防止反溅射和扩散。 可以通过掺杂通过层在衬底中形成晶体管。 可以在第一层下面提供另一层。 可以使用二氧化硅，碳化硅，氮化硅，钛，氮化钛，钛/氮化钛，氮化钽和碳化硅的层。

    Physical vapor deposition of nickel
    10.
    发明授权
    Physical vapor deposition of nickel 失效
    镍的物理气相沉积

    公开(公告)号：US06806172B1

    公开(公告)日：2004-10-19

    申请号：US09826078

    申请日：2001-04-05

    Applicant: Christy Mei-Chu Woo ,  Eric N. Paton ,  Susan Tover

    Inventor： Christy Mei-Chu Woo ,  Eric N. Paton ,  Susan Tover

    IPC: H01L21425

    CPC classification number: H01L29/665 ,  H01L21/324 ,  H01L29/7833

    Abstract: Nickel film formation is implemented by heating a deposition chamber during deposition of nickel on a substrate or between processing of two or more substrates or both. Embodiments include forming a nickel silicide on a composite having an exposed silicon surface by introducing the substrate to a PVD chamber having at least one heating element for heating the chamber and depositing a layer of nickel directly on the exposed silicon surface of the composite while concurrently heating the chamber with the heating element.

    Abstract translation: 通过在将镍沉积在基底上或在两个或更多个基底或两者的处理之间加热沉积室来实现镍膜形成。 实施例包括在具有暴露的硅表面的复合材料上形成硅化镍，通过将衬底引入具有至少一个用于加热室的加热元件的PVD室，并将镍层直接沉积在复合材料的暴露的硅表面上，同时加热 具有加热元件的室。

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