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    Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors
    1.
    发明授权
    Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors 有权
    电介质前体材料的电沉积用于嵌入栅极MOS晶体管

    公开(公告)号：US06300203B1

    公开(公告)日：2001-10-09

    申请号：US09679872

    申请日：2000-10-05

    申请人： Matthew S. Buynoski ,  Paul R. Besser ,  Qi Xang ,  Paul L. King ,  Eric N. Paton

    发明人： Matthew S. Buynoski ,  Paul R. Besser ,  Qi Xang ,  Paul L. King ,  Eric N. Paton

    IPC分类号： H01L21336

    CPC分类号： H01L21/28194 ,  H01L21/31683 ,  H01L29/517 ,  H01L29/66583

    摘要： High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolytically plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, on a semiconductor substrate, typically a silicon-based substrate, and then reacting the precursor layer with oxygen or with oxygen and the semiconductor substrate to form the at least one refractory or lanthanum series transition metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.

    摘要翻译： 通过电解电镀形成高质量的电介质层，例如由至少一种难熔或镧系列过渡金属氧化物或硅酸盐构成的高k电介质层，用作在叠层金属栅极MOS晶体管和CMOS器件中作为栅极绝缘体层 在半导体衬底（通常为硅基衬底）上包含至少一种难熔或镧系过渡金属的金属或金属基电介质前体层，然后使前体层与氧或氧和半导体衬底反应，形成 至少一种耐火材料或镧系列过渡金属氧化物或硅酸盐。 本发明的方法在至少形成栅极绝缘体层的初始阶段期间防止或至少基本上减少氧接触到衬底表面，从而最小化半导体衬底/栅极处的氧诱导表面状态的有害形成 绝缘子接口。

    Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors
    2.
    发明授权
    Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors 有权
    用于嵌入栅极MOS晶体管的介电材料前体材料的无电沉积

    公开(公告)号：US06559051B1

    公开(公告)日：2003-05-06

    申请号：US09679881

    申请日：2000-10-05

    申请人： Matthew S. Buynoski ,  Paul R. Besser ,  Paul L. King ,  Eric N. Paton ,  Qi Xang

    发明人： Matthew S. Buynoski ,  Paul R. Besser ,  Paul L. King ,  Eric N. Paton ,  Qi Xang

    IPC分类号： H01L2144

    CPC分类号： H01L21/28194 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66583

    摘要： High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, such as of Zr and/or Hf, on a silicon-based semiconductor substrate and then reacting the precursor layer with oxygen or with oxygen and the Si-based semiconductor substrate to form the at least one metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.

    摘要翻译： 通过无电镀法形成高质量电介质层，例如由至少一种耐火材料或镧系列过渡金属氧化物或硅酸盐构成的高k电介质层，用作叠层金属栅极MOS晶体管和CMOS器件中的栅极绝缘体层 金属或金属基电介质前体层，其在硅基半导体衬底上包含至少一种难熔或镧系过渡金属，例如Zr和/或Hf，然后使前体层与氧或氧与Si反应 的半导体衬底以形成至少一种金属氧化物或硅酸盐。 本发明的方法在至少形成栅极绝缘体层的初始阶段期间防止或至少基本上减少氧接触到衬底表面，从而最小化半导体衬底/栅极处的氧诱导表面状态的有害形成 绝缘子接口。

    Silicide gate transistors
    3.
    发明授权
    Silicide gate transistors 有权
    硅化物栅极晶体管

    公开(公告)号：US06368950B1

    公开(公告)日：2002-04-09

    申请号：US09734186

    申请日：2000-12-12

    申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    IPC分类号： H01L213205

    CPC分类号： H01L29/66545 ,  H01L21/28097

    摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.

    摘要翻译： 实现自对准金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆金属相互作用以形成自对准金属硅化物栅极来实现的。 在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。 除了凹部中硅的部分之外，除去硅。 通过操纵金属和自对准金属硅化物栅之间的蚀刻选择性来去除金属的剩余部分。

    Damascene NiSi metal gate high-k transistor
    8.
    发明授权
    Damascene NiSi metal gate high-k transistor 有权
    大马士革NiSi金属栅极高k晶体管

    公开(公告)号：US06475874B2

    公开(公告)日：2002-11-05

    申请号：US09731031

    申请日：2000-12-07

    申请人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    发明人： Qi Xiang ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    IPC分类号： H01L2120

    CPC分类号： H01L21/28194 ,  H01L21/28097 ,  H01L29/495 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

    摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying low temperature silicidation metal to interact to form the self-aligned low temperature metal silicide gate. A precursor having a temporary gate is used to form the self-aligned low temperature silicide gate. The remaining portions of the low temperature silicidation metal is removed by manipulating the etch selectivity between the low temperature silicidation metal and the self-aligned low temperature metal silicide gate.

    摘要翻译： 实现自对准低温金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆的低温硅化金属相互作用以形成自对准的低温金属来实现的 硅化物门 使用具有临时栅极的前体形成自对准低温硅化物栅极。 通过操纵低温硅化金属和自对准的低温金属硅化物栅极之间的蚀刻选择性来除去低温硅化金属的剩余部分。

    Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors
    9.
    发明授权
    Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors 有权
    用于嵌入栅极MOS晶体管的电介质前体材料的增强的无电沉积

    公开(公告)号：US06465334B1

    公开(公告)日：2002-10-15

    申请号：US09679369

    申请日：2000-10-05

    申请人： Matthew S. Buynoski ,  Paul R. Besser ,  Paul L. King ,  Eric N. Paton ,  Qi Xiang

    发明人： Matthew S. Buynoski ,  Paul R. Besser ,  Paul L. King ,  Eric N. Paton ,  Qi Xiang

    IPC分类号： H01L214763

    CPC分类号： H01L21/28194 ,  H01L21/288 ,  H01L21/31683 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

    摘要： High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are fabricated by forming an ultra-thin catalytic metal layer, e.g., a monolayer thick layer of Pd or Pd, on a Si-based semiconductor substrate, electrolessly plating on the catalytic layer comprising at least one refractory or lanthanum series transition metal or metal-based dielectric precursor layer, such as of Zr and/or Hf, and then reacting the precursor layer with oxygen or with oxygen and the semiconductor substrate to form the at least one high-k metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.

    摘要翻译： 通过形成高质量的电介质层，例如由至少一种难熔或镧系列过渡金属氧化物或硅酸盐构成的高k电介质层，用作在叠层金属栅极MOS晶体管和CMOS器件中用作栅极绝缘体层 超薄催化金属层，例如在Si基半导体衬底上的单层厚的Pd或Pd层，在包含至少一种难熔或镧系过渡金属或金属基电介质前体层的催化剂层上无电镀， 例如Zr和/或Hf，然后使前体层与氧或与氧和半导体衬底反应以形成至少一种高k金属氧化物或硅酸盐。 本发明的方法在至少形成栅极绝缘体层的初始阶段期间防止或至少基本上减少氧接触到衬底表面，从而最小化半导体衬底/栅极处的氧诱导表面状态的有害形成 绝缘子接口。

    Method of making silicide stop layer in a damascene semiconductor structure
    10.
    发明授权
    Method of making silicide stop layer in a damascene semiconductor structure 有权
    在大马士革半导体结构中制造硅化物阻挡层的方法

    公开(公告)号：US06458679B1

    公开(公告)日：2002-10-01

    申请号：US09780454

    申请日：2001-02-12

    申请人： Eric N. Paton ,  Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang ,  Paul L. King ,  John Clayton Foster

    发明人： Eric N. Paton ,  Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang ,  Paul L. King ,  John Clayton Foster

    IPC分类号： H01L213205

    CPC分类号： H01L29/66583 ,  H01L21/28052 ,  H01L29/4941

    摘要： A damascene gate semiconductor structure that is formed utilizing a silicide stop layer. Initially, a gate opening is provided in an insulating layer on a substrate. A first dielectric layer is deposited in the gate opening over the substrate. A silicide stop layer is then deposited in the gate opening over the first silicon layer. A second silicon layer is then deposited in the gate opening over the silicide stop layer. A metal or alloy layer is then deposited over the insulating and the second silicon layer. The damascene semiconductor structure is then temperature treated to react the metal or alloy layer with the second silicon layer to form a silicide layer. Any unreated metal or alloy is then removed from the metal or alloy layer.

    摘要翻译： 利用硅化物停止层形成的镶嵌栅极半导体结构。 首先，在基板上的绝缘层中设置栅极开口。 第一介电层沉积在衬底上的栅极开口中。 然后在第一硅层上的栅极开口中沉积硅化物阻挡层。 然后在硅化物停止层上的栅极开口中沉积第二硅层。 然后在绝缘层和第二硅层上沉积金属或合金层。 然后对镶嵌半导体结构进行温度处理以使金属或合金层与第二硅层反应形成硅化物层。 然后从金属或合金层中除去任何未反应的金属或合金。