Abstract:
Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage.
Abstract:
The present disclosure provides a TFT and a circuit structure to improve the characteristics of the threshold voltage drift of the TFT. The TFT includes a gate electrode, a semiconductor layer, an etch stop layer, and a source electrode and a drain electrode connected to the semiconductor layer. The TFT further includes a stopping structure arranged over the etch stop layer. The stopping structure is electrically isolated from the source electrode and the drain electrode, and an orthogonal projection of the stopping structure onto the etch stop layer at least partially overlaps an orthogonal projection of the semiconductor layer onto the etch stop layer. The present disclosure improves the characteristics of the threshold voltage drift of the TFT.
Abstract:
According to an embodiment of the present disclosure, a shift register unit may include: a first control module, configured to transmit a start signal to a first node; a second control module, configured to pull a potential of a second node to a potential different from a potential of the first node, under a control of a first clock signal; a carry output module, configured to output a carry signal according to the potential of the first node and the potential of the second node; and a shift output module, configured to output a shift signal according to the potential of the first node and the potential of the second node.
Abstract:
The present disclosure provides a TFT and a circuit structure to improve the characteristics of the threshold voltage drift of the TFT. The TFT includes a gate electrode, a semiconductor layer, an etch stop layer, and a source electrode and a drain electrode connected to the semiconductor layer. The TFT further includes a stopping structure arranged over the etch stop layer. The stopping structure is electrically isolated from the source electrode and the drain electrode, and an orthogonal projection of the stopping structure onto the etch stop layer at least partially overlaps an orthogonal projection of the semiconductor layer onto the etch stop layer. The present disclosure improves the characteristics of the threshold voltage drift of the TFT.
Abstract:
Embodiments of the present disclosure provide a shift register unit, a gate driving circuit, a driving method and a display apparatus, which can simplify the design of connection lines among the shift register units and thereby is beneficial to achieve a narrow frame of the product. The shift register unit comprises an input module connected to an input terminal, a first control signal terminal and a first node; an output module connected to a first node, a second node, a second control signal terminal, an output terminal and a second level terminal; and an output control module connected to the first node, the second node, the output terminal, a first level terminal and the second level terminal. The embodiments of the present disclosure are used to manufacture displays.
Abstract:
A display substrate and a display apparatus. The display substrate includes a display area provided with pixel circuits arranged in an array and a non-display area provided with M light emitting driving circuits, M control driving circuits and M reset driving circuits. Odd-numbered light emitting driving circuits are electrically connected with first and second light emitting clock signal lines, and even-numbered light emitting driving circuits are connected with third and fourth light emitting clock signal lines; and/or, odd-numbered control driving circuits are electrically connected with first and second control clock signal lines, and even-numbered control driving circuits are connected with third and fourth control clock signal lines; and/or, odd-numbered reset driving circuits are electrically connected with first and second reset clock signal lines, and even-numbered reset driving circuits are connected with third and fourth reset clock signal lines.
Abstract:
The display substrate includes a shift register arranged on a base substrate, and the shift register includes a plurality of stages of driving circuits; a plurality of stages of the driving circuit are provided in the driving circuit area of the base substrate; a stage of driving circuit area includes a first area and a second area, and the first area is provided with a first type of transistor included in the driving circuit, a second type of transistor included in the driving circuit is provided in the second area; one side of the first area is a side of the power line away from the second area, and the other side of the first area is a side close to the second area of an active layer of the first type of transistor close to the second area.
Abstract:
A display substrate is provided to include: a base substrate including a display area and a peripheral area surrounding the display area; pixel units in array are in the display area; a driving module is in the peripheral area and is configured to provide electrical signals for the pixel units, to control the pixel units to operate; the driving module includes driving circuits each provided with a corresponding operating signal line group in the peripheral area; the signal line group includes at least two operating signal lines connected to the corresponding driving circuit, to provide electrical signals thereto; the at least two operating signal lines include first and second clock signal lines; the first clock signal lines for at least two driving circuits are a same first clock signal line; and/or the second clock signal lines for the at least two driving circuits are a same second clock signal line.
Abstract:
A display substrate is provided. The display substrate includes a base substrate including a display region and a peripheral region, and a first scan driving circuit, a second scan driving circuit and a first power line arranged in sequence, and a first shielding layer and a second shielding layer sequentially arranged on a side of the second scan driving circuit away from the base substrate; the first shielding layer covers at least one transistor in the second scan driving circuit, and the second shielding layer covers at least one transistor of transistors in the second scan driving circuit except the at least one transistor covered by the first shielding layer; and the second shielding layer is also on a side of the first scan driving circuit away from the base substrate, and the second shielding layer covers at least one transistor in the first scan driving circuit.
Abstract:
Provided is a method for driving a display device including n rows of sub-pixels; the method includes: driving the first frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on a rows, from the 1st to ath rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−a) rows, from the (a+1)th to nth rows, of sub-pixels in a second darkness insertion sub-period driving a second frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on b rows, from the 1st to bth rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−b) rows, from the (b+1)th to nth rows, of sub-pixels in a second darkness insertion sub-period.