公开(公告)号：US20080144392A1

公开(公告)日：2008-06-19

申请号：US11691703

申请日：2007-03-27

Applicant: Sun-Kwon Kim ,  Byeong-Hoon Lee

Inventor： Sun-Kwon Kim ,  Byeong-Hoon Lee

IPC: G11C11/406

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: A method of operating a non-volatile memory device includes maintaining a write voltage at a predetermined voltage level for programming and/or erasing a memory cell of the non-volatile memory device during a time between execution of consecutive write operations. For example, the write voltage may be activated at the predetermined voltage level responsive to an initial write command, and discharge of the write voltage may be prevented responsive to a signal indicating consecutive write commands. Related devices are also discussed.

Abstract translation: 一种操作非易失性存储器件的方法包括将写入电压保持在预定电压电平，以便在执行连续写入操作之间的时间期间编程和/或擦除非易失性存储器件的存储器单元。 例如，可以响应于初始写入命令​​在预定电压电平下激活写入电压，并且可以根据指示连续写入命令的信号来防止写入电压的放电。 还讨论了相关设备。

公开(公告)号：US07127963B2

公开(公告)日：2006-10-31

申请号：US10241706

申请日：2002-09-12

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: B62D1/18

CPC classification number: B62D1/184

Abstract: The present invention relates to a tilt device for a vehicular steering column, which permits a lock slider cooperating with an operating lever to regulate pivoting of a movable gear by simplifying the engagement structure between the movable gear and a fixed gear to reduce the number of parts and enhance assembling ability, thereby reducing manufacturing cost. The tilt device of the invention also minimizes the operating force of the operating lever while elevating the coupling force between the operating lever and a lock slider so as to improve convenience of users.

公开(公告)号：US06944085B2

公开(公告)日：2005-09-13

申请号：US10376757

申请日：2003-02-27

Applicant: Byeong-Hoon Lee ,  Seung-Keun Lee

Inventor： Byeong-Hoon Lee ,  Seung-Keun Lee

IPC: G11C16/06 ,  G11C16/04 ,  G11C29/00 ,  G11C29/04 ,  G11C8/00

CPC classification number: G11C29/789 ,  G11C16/0441 ,  G11C29/808

Abstract: A redundancy circuit embedded in the semiconductor memory device includes a sector selector and a bit line selector. The bit line selector repairs defective bit lines and the sector selector repairs defective global bit lines and selectively repairs defective bit lines. The sector selector includes a fixed address cell storage box for storing addresses of the defective bit lines and a flexible address cell storage box for storing addresses of the defective global bit lines. The circuit area is minimized since the coding unit corresponding to a sector address is not included in the bit line selector. The repair rate of defective bit lines is improved since the sector selector operates selectively as the bit line selector.

Abstract translation: 嵌入在半导体存储器件中的冗余电路包括扇区选择器和位线选择器。 位线选择器修复有缺陷的位线，并且扇区选择器修复缺陷的全局位线，并选择性地修复有缺陷的位线。 扇区选择器包括用于存储有缺陷位线的地址的固定地址单元存储盒和用于存储缺陷全局位线的地址的灵活地址单元存储盒。 由于与扇区地址相对应的编码单元不包括在位线选择器中，所以电路区域被最小化。 由于扇区选择器选择性地作为位线选择器操作，故障位线的修复率得到改善。

公开(公告)号：US06690227B2

公开(公告)日：2004-02-10

申请号：US10055269

申请日：2002-01-22

Applicant: Byeong-Hoon Lee ,  Seung-Keun Lee ,  Seung-Won Lee

Inventor： Byeong-Hoon Lee ,  Seung-Keun Lee ,  Seung-Won Lee

IPC: G05F110

CPC classification number: H02M3/073 ,  H02M2003/078

Abstract: A charge pump circuit includes a plurality of serially connected pump stages. Each pump stage includes current paths connected between a gate terminal of a charge transfer transistor and a drain terminal thereof. One of the charge transfer paths allows charges to be transferred from the drain terminal to the gate terminal while the other path allows charges to be transferred from the gate terminal to the drain terminal. The charge pump circuit can generate a high target voltage using a very low power supply voltage (e.g., 2V or lower).

Abstract translation: 电荷泵电路包括多个串联连接的泵级。 每个泵级包括连接在电荷转移晶体管的栅极端子和其漏极端子之间的电流路径。 电荷转移路径之一允许电荷从漏极端子传送到栅极端子，而另一路径允许电荷从栅极端子传输到漏极端子。 电荷泵电路可以使用非常低的电源电压（例如2V或更低）产生高目标电压。

公开(公告)号：US06665229B2

公开(公告)日：2003-12-16

申请号：US10122131

申请日：2002-04-11

Applicant: Byeong-Hoon Lee ,  Seung-Keun Lee

Inventor： Byeong-Hoon Lee ,  Seung-Keun Lee

IPC: G11C800

CPC classification number: G11C8/14 ,  G11C8/08 ,  G11C8/10 ,  G11C16/08 ,  G11C16/30 ,  G11C2216/18

Abstract: Semiconductor memory device row decoder structures have reduced layout area. A structure for erasing memory cells coupled to a single bitline includes a single bias driver for these cells, and a plurality of local voltage level converters coupled to the bias driver. At least one word line driver is coupled to each local level converter, to erase at least one of the memory cells. A global word line is also coupled to the word line driver. A method for erasing these memory cells includes biasing the local level converter, for powering in turn a component of the word line driver. In addition, an existing global word line driver powers another component of the word line driver, thus resulting in reduced design requirements for the local level converter.

Abstract translation: 半导体存储器件行解码器结构具有减小的布局面积。 用于擦除耦合到单个位线的存储器单元的结构包括用于这些单元的单个偏置驱动器和耦合到偏置驱动器的多个局部电压电平转换器。 至少一个字线驱动器耦合到每个局部电平转换器，以擦除至少一个存储器单元。 全局字线也耦合到字线驱动器。 用于擦除这些存储单元的方法包括偏置本地电平转换器，从而依次为字线驱动器的部件供电。 此外，现有的全局字线驱动器为字线驱动器的另一个组件供电，从而导致局部级转换器的设计要求降低。

公开(公告)号：US06490199B2

公开(公告)日：2002-12-03

申请号：US09867899

申请日：2001-05-30

Applicant: Byeong-Hoon Lee ,  Young-Ho Lim

Inventor： Byeong-Hoon Lee ,  Young-Ho Lim

IPC: G11C1606

CPC classification number: G11C16/28

Abstract: A sense amplifier circuit for a flash memory device of the present invention includes first and second pre-charge circuits for pre-charging a data line (or bit line connected electrically to the data line). The first and second pre-charge circuits are each connected to the data line. The first pre-charge circuit provides a current changed by a fluctuation of the data line voltage to the data line, and the second pre-charge circuit provides a constant voltage regardless of the fluctuation of the data line voltage to the data line. The sense amplifier minimizes the time required to pre-charge the data line (or bit line) to a desired voltage.

Abstract translation: 本发明的闪存器件的读出放大器电路包括用于对数据线（或与数据线电连接的位线）进行预充电的第一和第二预充电电路。 第一和第二预充电电路各自连接到数据线。 第一预充电电路提供由数据线电压向数据线的波动而改变的电流，并且第二预充电电路提供恒定电压，而不管数据线电压对数据线的波动。 读出放大器将数据线（或位线）预充电所需的时间最小化到所需的电压。