公开(公告)号：US07543116B2

公开(公告)日：2009-06-02

申请号：US11342951

申请日：2006-01-30

申请人： Guy L. Guthrie ,  John T. Hollaway, Jr. ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthrie ,  John T. Hollaway, Jr. ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0822 ,  G06F12/0804 ,  G06F12/0831

摘要： A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain contains a memory controller, an associated system memory having a target memory block identified by a target address, and a domain indicator indicating whether the target memory block is cached outside the first coherency domain. During operation, the first coherency domain receives a flush operation broadcast to the first and second coherency domains, where the flush operation specifies the target address of the target memory block. The first coherency domain also receives a combined response for the flush operation representing a system-wide response to the flush operation. In response to receipt in the first coherency domain of the combined response, a determination is made if the combined response indicates that a cached copy of the target memory block may remain within the data processing system. In response to a determination that the combined response indicates that a cached copy of the target memory block may remain in the data processing system, the domain indicator is updated to indicate that the target memory block is cached outside of the first coherency domain.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 第一相干域包括存储器控制器，具有由目标地址标识的目标存储器块的相关系统存储器，以及指示目标存储器块是否被高速缓存在第一相干域之外的域指示符。 在操作期间，第一相干域接收向第一和第二相干域广播的刷新操作，其中刷新操作指定目标存储器块的目标地址。 第一个相干域还接收表示对刷新操作的系统范围响应的刷新操作的组合响应。 响应于在组合响应的第一相关域中的接收，确定组合响应是否指示目标存储器块的高速缓存副本可能保留在数据处理系统内。 响应于确定组合响应指示目标存储器块的高速缓存副本可能保留在数据处理系统中，则域指示符被更新以指示目标存储器块被高速缓存在第一相干域之外。

公开(公告)号：US07475196B2

公开(公告)日：2009-01-06

申请号：US11388001

申请日：2006-03-23

申请人： Ravi K. Arimilli ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： Ravi K. Arimilli ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F13/00

CPC分类号： G06F12/0822 ,  G06F12/084

摘要： A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor core that indicates a target memory block to be initialized, a cache memory in the first coherency domain determines a coherency state of the target memory block with respect to the cache memory. In response to the determination, the cache memory selects a scope of broadcast of an initialization request identifying the target memory block. A narrower scope including the first coherency domain and excluding the second coherency domain is selected in response to a determination of a first coherency state, and a broader scope including the first coherency domain and the second coherency domain is selected in response to a determination of a second coherency state. The cache memory then broadcasts an initialization request with the selected scope. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value.

摘要翻译： 数据处理系统至少包括第一和第二相干域，每个域包括至少一个处理器核和存储器。 响应于指示要初始化的目标存储器块的处理器核心的初始化操作，第一相干域中的高速缓冲存储器确定目标存储器块相对于高速缓存存储器的一致性状态。 响应于该确定，高速缓存存储器选择识别目标存储器块的初始化请求的广播范围。 响应于第一相关性状态的确定而选择包括第一相关域并且排除第二相关性域的较窄范围，并且响应于确定第一相关性域的第一相关性域和第二相关域 第二一致性状态。 然后，高速缓冲存储器播放具有所选范围的初始化请求。 响应于初始化请求，将目标存储器块在数据处理系统的存储器内初始化为初始化值。

公开(公告)号：US07454580B2

公开(公告)日：2008-11-18

申请号：US11380020

申请日：2006-04-25

申请人： Ravi K. Arimilli ,  Thomas M. Capasso ,  Robert A. Cargnoni ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke

发明人： Ravi K. Arimilli ,  Thomas M. Capasso ,  Robert A. Cargnoni ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34

CPC分类号： G06F9/3842 ,  G06F9/3851 ,  G06F9/544

摘要： A data processing system includes a processor core and a memory subsystem. The memory subsystem includes a store queue having a plurality of entries, where each entry includes an address field for holding the target address of store operation, a data field for holding data for the store operation, and a virtual sync field indicating a presence or absence of a synchronizing operation associated with the entry. The memory subsystem further includes a store queue controller that, responsive to receipt at the memory subsystem of a sequence of operations including a synchronizing operation and a particular store operation, places a target address and data of the particular store operation within the address field and data field, respectively, of an entry in the store queue and sets the virtual sync field of the entry to represent the synchronizing operation, such that a number of store queue entries utilized is reduced.

摘要翻译： 数据处理系统包括处理器核心和存储器子系统。 存储器子系统包括具有多个条目的存储队列，其中每个条目包括用于保存存储操作的目标地址的地址字段，用于保存用于存储操作的数据的数据字段和指示存在或不存在的虚拟同步字段 与该条目相关联的同步操作。 存储器子系统还包括存储队列控制器，其响应于在存储器子系统处的接收包括同步操作和特定存储操作的一系列操作，将特定存储操作的目标地址和数据放置在地址字段和数据中 字段，并且设置条目的虚拟同步字段以表示同步操作，使得减少使用的存储队列条目的数量。

公开(公告)号：US07454578B2

公开(公告)日：2008-11-18

申请号：US11055697

申请日：2005-02-10

申请人： James S. Fields, Jr. ,  Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Phillip G. Williams

发明人： James S. Fields, Jr. ,  Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Phillip G. Williams

IPC分类号： G06F13/00

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation targeting a request address allocated to the memory from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains. The master selects the scope based, at least in part, upon whether the memory belongs to the first coherency domain and performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.

摘要翻译： 高速缓存一致数据处理系统包括存储器和至少第一和第二一致性域，每个域包括第一和第二高速缓存存储器中的相应一个。 第一相干域中的主机从仅包括第一相关域的第一范围和包括第一和第二相干域的第二范围中选择针对分配给存储器的请求地址的操作的初始广播的范围。 主设备至少部分地基于所述存储器是否属于第一相关域并且使用所选择的范围来执行在高速缓存相干数据处理系统内的操作的初始广播来选择所述范围。

公开(公告)号：US07451277B2

公开(公告)日：2008-11-11

申请号：US11388017

申请日：2006-03-23

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F2212/507

摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping an exclusive access operation, the exclusive access request specifying a target address matching the address tag and indicating a relative domain location of a requester that initiated the exclusive access operation, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and whether a target memory block associated with the address tag is cached within the first coherency domain upon successful completion of the exclusive access operation based upon the relative location of the requestor.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 在数据处理系统的第一相关域内的第一高速缓冲存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态， 存储位置不包含有效数据。 响应于窥探独占访问操作，专用访问请求指定与地址标签匹配的目标地址，并且指示发起独占访问操作的请求者的相对域位置，第一高速缓存存储器从第一数据更新相关性状态字段 - 无效的一致性状态到指示地址标签有效的第二数据无效一致性状态，存储位置不包含有效数据，以及与地址标签相关联的目标存储器块是否被缓存在第一相关域内 基于请求者的相对位置成功完成独占访问操作。

公开(公告)号：US07447844B2

公开(公告)日：2008-11-04

申请号：US11457322

申请日：2006-07-13

申请人： Leo J. Clark ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： Leo J. Clark ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/1425 ,  G06F12/0817 ,  G06F12/0897

摘要： A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.

摘要翻译： 处理单元包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。 高速缓冲存储器包括数据阵列，数据阵列的内容目录。 缓存存储器还包括服务于第一组存储器访问请求的一个或多个状态机，通过参考数据阵列和固定时间表上的目录来指导第二组存储器访问请求的服务的仲裁器，地址冲突逻辑 其通过检测和发出第二组中的活动存储器访问请求与后续存储器访问请求之间的地址冲突以及耦合到地址冲突逻辑的调度逻辑来保护第二组中的存储器访问请求。 调度逻辑将第一组中的存储器访问请求分派到一个或多个状态机用于服务，并且向仲裁器发出信号，以根据固定的时间表对第二组中的存储器访问请求进行直接服务。

公开(公告)号：US07444494B2

公开(公告)日：2008-10-28

申请号：US11140821

申请日：2005-05-31

申请人： Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0833 ,  G06F2212/507

摘要： According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.

摘要翻译： 根据数据处理的方法，保持预测器，其指示在数据处理系统的互连上发送的一个或多个先前操作的广播的历史范围。 通过参考预测器预测性地选择后续操作的广播范围。

公开(公告)号：US20080225863A1

公开(公告)日：2008-09-18

申请号：US12124639

申请日：2008-05-21

申请人： Ravi K. Arimilli ,  Benjiman L. Goodman ,  Guy L. Guthrie ,  Praveen S. Reddy ,  William J. Starke

发明人： Ravi K. Arimilli ,  Benjiman L. Goodman ,  Guy L. Guthrie ,  Praveen S. Reddy ,  William J. Starke

IPC分类号： H04L12/56

CPC分类号： G06F15/16

摘要： A data processing system includes a first plane including a first plurality of processing nodes, each including multiple processing units, and a second plane including a second plurality of processing nodes, each including multiple processing units. The data processing system also includes a plurality of point-to-point first tier links. Each of the first plurality and second plurality of processing nodes includes one or more first tier links among the plurality of first tier links, where the first tier link(s) within each processing node connect a pair of processing units in the same processing node for communication. The data processing system further includes a plurality of point-to-point second tier links. At least a first of the plurality of second tier links connects processing units in different ones of the first plurality of processing nodes, at least a second of the plurality of second tier links connects processing units in different ones of the second plurality of processing nodes, and at least a third of the plurality of second tier links connects a processing unit in the first plane to a processing unit in the second plane.

摘要翻译： 数据处理系统包括包括第一多个处理节点的第一平面，每个处理节点包括多个处理单元，以及包括第二多个处理节点的第二平面，每个处理节点包括多个处理单元。 数据处理系统还包括多个点对点第一层链路。 第一多个处理节点和第二多个处理节点中的每一个包括多个第一层链路之中的一个或多个第一层链路，其中每个处理节点内的第一层链路连接相同处理节点中的一对处理单元，用于 通讯。 数据处理系统还包括多个点到点第二层链路。 所述多个第二层链路中的至少第一层连接所述第一多个处理节点中的不同处理节点中的处理单元，所述多个第二层链路中的至少一个链接连接所述第二多个处理节点中的不同处理节点中的处理单元， 并且所述多个第二层链路中的至少三分之一链路将所述第一平面中的处理单元连接到所述第二平面中的处理单元。

公开(公告)号：US20080215821A1

公开(公告)日：2008-09-04

申请号：US12103564

申请日：2008-04-15

申请人： Jason F. Cantin ,  James S. Fields ,  Steven R. Kunkel ,  William J. Starke

发明人： Jason F. Cantin ,  James S. Fields ,  Steven R. Kunkel ,  William J. Starke

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0811 ,  G06F12/0813

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.

摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓冲存储器，并且第二相干域包括相干第二高速缓冲存储器。 数据处理系统的第一相干域内的第一高速缓冲存储器在与地址标签和一致性状态字段相关联的存储位置中保存存储器块。 相关性状态字段被设置为指示地址标签有效的状态，存储位置不包含有效数据，并且该存储器块可能仅在第一相干域内被缓存。

公开(公告)号：US20080201534A1

公开(公告)日：2008-08-21

申请号：US12114786

申请日：2008-05-04

申请人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F13/1605 ,  G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/reorder unit is full in which case the new snoop request is transmitted to a second unit configured to transmit a request to retry resending the new snoop request. Snoop requests have a higher priority than requests from processors and snoop requests are selected by the arbitration mechanism over processor requests unless the arbitration mechanism requests otherwise (“stall request”) to the stall/reorder unit. By snoop requests having a higher priority than processor requests, the number of snoop requests rejected is reduced. By having the arbitration mechanism issue a stall request, the processor will not be starved.

摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 监听请求被输入到停止/重新排序单元的第一可用锁存器中，除非停止/重新排序单元已满，在这种情况下，新的窥探请求被发送到被配置为发送重新发送新的窥探请求的请求的第二单元。 侦听请求具有比来自处理器的请求更高的优先级，并且仲裁机制通过处理器请求选择侦听请求，除非仲裁机制另请求（“停止请求”）到停止/重新排序单元。 通过具有比处理器请求更高优先级的侦听请求，减少了被拒绝的侦听请求的数量。 通过使仲裁机制发出停顿请求，处理器不会饿死。