公开(公告)号：US5670407A

公开(公告)日：1997-09-23

申请号：US791507

申请日：1997-01-30

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/92 ,  Y10S438/947

摘要： The present invention is a method of fabricating a toothed-shape capacitor node in a semiconductor DRAM circuit. This invention utilizes dot silicon as an etching mask. Next, the polysilicon is oxidized and removed to form trenches in the bottom storage of the capacitor. Thus, a toothed-shape capacitor node is formed in semiconductor circuit.

摘要翻译： 本发明是在半导体DRAM电路中制造齿形电容器节点的方法。 本发明利用点硅作为蚀刻掩模。 接下来，多晶硅被氧化并去除，以在电容器的底部存储器中形成沟槽。 因此，在半导体电路中形成齿形电容器节点。

公开(公告)号：US5670405A

公开(公告)日：1997-09-23

申请号：US791504

申请日：1997-01-30

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/02 ,  H01L21/70

CPC分类号： H01L28/92 ,  Y10S148/138

摘要： A method of manufacturing a capacitor for use in semiconductor memories is disclosed herein. The present invention includes forming a silicon oxide layer as an etching mask to etch a polysilicon layer to form a bottom storage node of a capacitor. The silicon oxide layer is formed from the thermal annealing of oxygen doped dot silicon.

摘要翻译： 本文公开了制造用于半导体存储器的电容器的方法。 本发明包括形成氧化硅层作为蚀刻掩模以蚀刻多晶硅层以形成电容器的底部存储节点。 氧化硅层由氧掺杂点硅的热退火形成。

公开(公告)号：US5663093A

公开(公告)日：1997-09-02

申请号：US665328

申请日：1996-06-17

申请人： Horng-Huei Tseng ,  Chih-Yuan Lu

发明人： Horng-Huei Tseng ,  Chih-Yuan Lu

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for manufacturing a cylindrical stacked capacitor having a central spine for a DRAM using only one photo mask is provided. The invention uses sidewall spacers and selective etching techniques to form a low cost, simple to manufacture, high capacitance capacitor and DRAM cell. A substrate having source regions, drain regions and gate electrode structures is provided. An insulating layer with a contact opening is formed over the substrate surface. A first conductive layer and a first dielectric layer are formed over the insulating layer. The first dielectric layer and first conductive layer are etched forming a central spine over the contact opening. The etched first dielectric layer forms a dielectric cap over central spine. Dielectric spacers are formed on the sidewall of the central spine and the dielectric cap. The remaining portions of the first conductive layer are anisotropically etched using the dielectric spacers and the dielectric cap as a mask. Conductive spacers are formed on the sidewalls of the dielectric spacers. The dielectric cap and the dielectric spacers are selectively etched thereby forming a crown shaped storage node having a central spine. A capacitor dielectric layer and a top electrode are formed over the crown shaped storage node and the insulating layer forming a crown shaped capacitor.

摘要翻译： 提供一种制造具有仅使用一个光掩模的DRAM的具有中央脊的圆柱形堆叠电容器的方法。 本发明使用侧壁间隔物和选择性蚀刻技术来形成低成本，易于制造的高容量电容器和DRAM单元。 提供具有源极区，漏极区和栅电极结构的衬底。 在衬底表面上形成具有接触开口的绝缘层。 第一导电层和第一介电层形成在绝缘层上。 第一电介质层和第一导电层被蚀刻在接触开口上形成中心脊。 蚀刻的第一介电层在中心脊上形成电介质盖。 电介质隔离物形成在中心脊和绝缘帽的侧壁上。 使用电介质间隔物和电介质盖作为掩模对第一导电层的剩余部分进行各向异性蚀刻。 导电间隔物形成在电介质间隔物的侧壁上。 选择性地蚀刻电介质盖和介电间隔物，从而形成具有中心脊的冠形存储节点。 电容器电介质层和顶部电极形成在冠形存储节点之上，绝缘层形成冠状电容器。

公开(公告)号：US5631480A

公开(公告)日：1997-05-20

申请号：US494637

申请日：1995-06-23

申请人： Horng-Huei Tseng ,  Chih-Yuan Lu

发明人： Horng-Huei Tseng ,  Chih-Yuan Lu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L28/82 ,  H01L28/86

摘要： A method, and resultant structure, is described for fabricating a DRAM (Dynamic Random Access Memory) cell having a stack capacitor with a ladder storage node, connected to a MOS (Metal Oxide Semiconductor) transistor with source and drain regions, to form a DRAM cell. A bottom electrode is connected to and extends up from the source region of the transistor, and has a top surface with a central cavity, and side surfaces extending down from the top surface in a step-like manner. These step-like sides are formed by a repeated two-step process of removing a portion of the vertical walls of a photoresist mask and removing a portion of the top surface of a layer of polysilicon from which the bottom electrode is formed. There is a capacitor dielectric over the bottom electrode. A top electrode is formed over the capacitor dielectric.

摘要翻译： 描述了一种用于制造具有梯形存储节点的堆叠电容器的DRAM（动态随机存取存储器）单元，其连接到具有源极和漏极区域的MOS（金属氧化物半导体）晶体管，以形成DRAM 细胞。 底部电极连接到晶体管的源极区域并且从晶体管的源极区域向上延伸，并具有具有中心空腔的顶表面，并且侧表面以阶梯状方式从顶表面向下延伸。 通过重复的两步法除去光致抗蚀剂掩模的垂直壁的一部分并且去除形成底部电极的多晶硅层的顶表面的一部分，形成这些阶梯状侧。 底部电极上有一个电容电介质。 在电容器电介质上形成顶部电极。

公开(公告)号：US5595926A

公开(公告)日：1997-01-21

申请号：US267405

申请日：1994-06-29

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/02 ,  H01L21/334 ,  H01L21/8242 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10861 ,  H01L28/82 ,  H01L29/66181

摘要： A method, and resultant structure, is described for fabricating a DRAM trench capacitor with a single pillar recessed below the level of the top surface of the silicon substrate in which it is formed. First and second insulating layers are formed over the silicon substrate, and patterned to form an opening to the silicon substrate. A portion of the silicon substrate is removed in the region defined by the opening, whereby a first trench is formed. Sidewall spacers are formed along the sides of the first trench from a third insulating layer. A first pillar is formed after depositing a first conductive layer between the sidewall spacers and over the trench and removing the first conductive layer except within the first trench. The sidewall spacers are removed. A portion of the silicon substrate in the first trench is removed that is not vertically masked by the pillar, and simultaneously a portion top of the pillar is removed, whereby a second trench and second pillar are formed at a greater depth in the silicon substrate. The remainder of the second insulating layer is also removed. A capacitor dielectric is formed in the second trench over the second pillar. A second conducting layer is formed over the dielectric layer and removed in the region outside of the trench to form the top capacitor electrode.

摘要翻译： 描述了一种用于制造DRAM沟槽电容器的方法和结果，该DRAM沟槽电容器具有在其所形成的硅衬底的顶表面的下方凹陷的单个柱体。 第一和第二绝缘层形成在硅衬底上，并被图案化以形成到硅衬底的开口。 在由开口限定的区域中去除硅衬底的一部分，从而形成第一沟槽。 从第三绝缘层沿着第一沟槽的侧面形成侧壁间隔物。 在第一导电层沉积在侧壁间隔物之间​​并在沟槽之上并除去第一沟槽以外的第一导电层时形成第一柱。 去除侧壁间隔物。 第一沟槽中的硅衬底的一部分被去除而不被柱垂直掩蔽，同时去除柱的一部分顶部，从而在硅衬底中形成更大深度的第二沟槽和第二柱。 第二绝缘层的其余部分也被去除。 在第二支柱上的第二沟槽中形成电容器电介质。 在电介质层上形成第二导电层，并在沟槽外部的区域中去除第二导电层以形成顶部电容器电极。

公开(公告)号：US5587338A

公开(公告)日：1996-12-24

申请号：US428493

申请日：1995-04-27

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76877

摘要： A process for creating a polysilicon contact stud, to connect overlying metallizations, to underlying active device regions in a semiconductor substrate, has been developed. After filling a contact hole with insitu doped polysilicon, and overlying with a titanium film, an anneal cycle is performed to convert the unwanted portions of polysilicon to titanium silicide. The silicide is then selectively removed, leaving polysilicon only in the contact hole, thus resulting in the desired stud configuration.

摘要翻译： 已经开发了用于创建多晶硅接触柱以将覆盖的金属化连接到半导体衬底中的底层有源器件区域的工艺。 在用原位掺杂多晶硅填充接触孔并且用钛膜覆盖之后，执行退火循环以将多晶硅的不想要部分转化为硅化钛。 然后选择性地去除硅化物，仅在接触孔中留下多晶硅，从而产生所需的螺柱结构。

公开(公告)号：US5573967A

公开(公告)日：1996-11-12

申请号：US811537

申请日：1991-12-20

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  Y10S438/967

摘要： A method is described for fabricating a DRAM having a fin-type stacked capacitor. The method begins by forming a MOSFET source/drain and gate structure on a silicon substrate. The gate electrode is composed of a first polysilicon layer. A first insulator layer composed at least in part of silicon nitride is formed over the device and field oxide areas. The fin-type stacked capacitors are now formed by depositing a second polysilicon layer over the device and field oxide areas. Alternating layers of polysilicon and insulator are deposited over the device and field oxide areas with the first polysilicon layer being in contact to the device areas for electrical contact and the last polysilicon layer being the topmost of the alternating layers. The stack of alternating polysilicon and insulator layers are now patterned to form the basis of the stacked capacitors. The exposed edges of the insulator layers are controlably and laterally isotropic etched to increase the planned surface area of the capacitor by forming fin-type structures. A fourth polysilicon layer is deposited over the device and field oxide areas to complete the lower electrode of the stacked capacitor. A capacitor dielectric layer is formed over the lower electrode of the capacitor and the top polysilicon electrode is deposited thereover to complete the stacked capacitor.

摘要翻译： 描述了一种用于制造具有鳍式叠层电容器的DRAM的方法。 该方法开始于在硅衬底上形成MOSFET源极/漏极和栅极结构。 栅电极由第一多晶硅层构成。 至少部分由氮化硅构成的第一绝缘体层形成在器件和场氧化物区域上。 翅片型堆叠电容器现在通过在器件和场氧化物区域上沉积第二多晶硅层而形成。 多晶硅和绝缘体的交替层沉积在器件和场氧化物区域上，其中第一多晶硅层与器件区域接触以进行电接触，并且最后的多晶硅层是交替层的最顶层。 交替的多晶硅和绝缘体层的堆叠现在被图案化以形成叠层电容器的基础。 绝缘体层的暴露边缘可控地和横向各向同性地蚀刻，以通过形成鳍型结构来增加电容器的计划表面积。 在器件和场氧化物区域上沉积第四多晶硅层以完成堆叠电容器的下电极。 在电容器的下电极上形成电容器电介质层，并且顶部多晶硅电极沉积在其上以完成堆叠的电容器。

公开(公告)号：US5330928A

公开(公告)日：1994-07-19

申请号：US951794

申请日：1992-09-28

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10817

摘要： A method is described for fabricating a dynamic random access memory having a high capacitance stacked capacitor. Gate structures and associated source/drain structures are formed within the device areas. A first silicon oxide layer is formed over the device and field oxide areas. The stacked capacitors are now formed by first depositing a thick second polysilicon layer over the device and field oxide areas. Openings are formed to the desired source/drain structures by etching through the second oxide, second polysilicon, and first oxide layers. Cavities are formed between the first and second oxide layers by laterally etching the second polysilicon layer. A third polysilicon layer is deposited over the device and field oxide areas. The second and third polysilicon layers and the first and second oxide layers are patterned so as to have their remaining portions over the planned capacitor areas. The layers are etched leaving the third polysilicon layer as the bottom storage node electrode contacting the source/drain structures. The remaining second and third polysilicon layers form the storage node of the capacitor. A capacitor dielectric layer is formed over the bottom electrode polysilicon layer. A contact polysilicon layer is deposited as the top plate electrode and the contact polysilicon layer and the dielectric layer are patterned to complete the stacked capacitor.

摘要翻译： 描述了一种用于制造具有高电容堆叠电容器的动态随机存取存储器的方法。 栅极结构和相关的源极/漏极结构形成在器件区域内。 在器件和场氧化物区域上形成第一氧化硅层。 现在通过首先在器件和场氧化物区域上沉积厚的第二多晶硅层来形成堆叠的电容器。 通过蚀刻通过第二氧化物，第二多晶硅和第一氧化物层，将所希望的源极/漏极结构形成开口。 通过横向蚀刻第二多晶硅层，在第一和第二氧化物层之间形成空穴。 在器件和场氧化物区域上沉积第三多晶硅层。 图案化第二和第三多晶硅层以及第一和第二氧化物层，使其剩余部分在规划的电容器区域上。 当底部存储节点电极接触源极/漏极结构时，这些层被蚀刻离开第三多晶硅层。 剩余的第二和第三多晶硅层形成电容器的存储节点。 电容器电介质层形成在底部电极多晶硅层上。 沉积接触多晶硅层作为顶板电极，并且对接触多晶硅层和电介质层进行图案化以完成叠层电容器。

公开(公告)号：US5126916A

公开(公告)日：1992-06-30

申请号：US810832

申请日：1991-12-20

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L27/108

CPC分类号： H01L27/10817

摘要： A DRAM having stacked high capacitance capacitors formed by depositing a thick undoped polysilicon layer over field oxide areas thereon, patterning the polysilicon layer so as to have portions over the planned stacked capacitor areas, forming a silicon oxide layer on the exposed surface of the polysilicon, removing the silicon oxide layer from horizontal surfaces of the polysilicon layer by anisotropic etching, removing the polysilicon layer by isotropic etching leaving vertical silicon oxide structures, and forming openings to desired source/drain structures of the DRAM using lithography and etching. A bottom electrode polysilicon layer is deposited over the device and field oxide areas to make contact to the source/drain structures. A capacitor dielectric layer is formed over the bottom electrode polysilicon layer. A contact polysilicon layer is deposited as the top storage node electrode and the contact polysilicon layer and the dielectric layers are patterned.

摘要翻译： 通过在其上的场氧化物区域上沉积厚的未掺杂的多晶硅层而形成堆叠的高电容电容器的DRAM，对多晶硅层进行构图以便在预定的叠层电容器区域上形成部分，在多晶硅的暴露表面上形成氧化硅层， 通过各向异性蚀刻从多晶硅层的水平表面去除氧化硅层，通过各向同性蚀刻去除多晶硅层，留下垂直的氧化硅结构，以及使用光刻和蚀刻在DRAM的所需源极/漏极结构上形成开口。 底部电极多晶硅层沉积在器件和场氧化物区域上以与源极/漏极结构接触。 电容器电介质层形成在底部电极多晶硅层上。 沉积接触多晶硅层作为顶部存储节点电极，并且接触多晶硅层和电介质层被图案化。

公开(公告)号：US08368220B2

公开(公告)日：2013-02-05

申请号：US11252498

申请日：2005-10-18

申请人： David Lu ,  Horng-Huei Tseng ,  Syun-Ming Jang

发明人： David Lu ,  Horng-Huei Tseng ,  Syun-Ming Jang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anchored conductive damascene buried in a multi-density dielectric layer and method for forming the same, the anchored conductive damascene including a dielectric layer with an opening extending through a thickness of the dielectric layer; wherein the dielectric layer comprises at least one relatively higher density portion and a relatively lower density portion, the relatively lower density portion forming a contiguous major portion of the dielectric layer; and, wherein the opening in the relatively lower density portion has a lateral dimension relatively larger compared to the relatively higher density portion to form anchoring steps.

摘要翻译： 埋置在多密度电介质层中的锚定导电镶嵌体及其形成方法，所述锚定导电镶嵌体包括具有延伸穿过介电层厚度的开口的介电层; 其中所述电介质层包括至少一个相对较高密度的部分和相对较低的密度部分，所述较低密度部分形成所述电介质层的连续主要部分; 并且其中相对较低密度部分中的开口具有与相对较高密度部分相比较大的横向尺寸以形成锚固步骤。