公开(公告)号：US08999764B2

公开(公告)日：2015-04-07

申请号：US11836819

申请日：2007-08-10

Applicant: Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

Inventor： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

IPC: H01L21/00 ,  H01L23/532 ,  H01L23/556

CPC classification number: H01L23/5329 ,  H01L23/556 ,  H01L2924/0002 ,  Y10S438/958 ,  Y10S438/967 ,  H01L2924/00

Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

Abstract translation: 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。

公开(公告)号：US20110253982A1

公开(公告)日：2011-10-20

申请号：US13126381

申请日：2009-10-28

Applicant: Deli Wang ,  Cesare Soci ,  Xinyu Bao ,  Wei Wei ,  Yi Jing ,  Ke Sun

Inventor： Deli Wang ,  Cesare Soci ,  Xinyu Bao ,  Wei Wei ,  Yi Jing ,  Ke Sun

IPC: H01L29/775 ,  H01L21/20 ,  H01L29/66 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L21/0262 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02573 ,  H01L21/02603 ,  H01L21/02636 ,  H01L27/0605 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/7784 ,  H01L29/88 ,  H01L31/035281 ,  H01L31/03529 ,  H01L31/074 ,  H01L33/08 ,  H01L33/20 ,  H01L33/32 ,  Y02E10/50 ,  Y10S438/938 ,  Y10S438/967 ,  Y10S438/974 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764 ,  Y10S977/765 ,  Y10S977/813 ,  Y10S977/815 ,  Y10S977/819 ,  Y10S977/825

Abstract: Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures. An array of Group III-V nanowire structures is embedded in polymer. A fabrication method forms the vertical nanowires on a substrate, e.g., a silicon substrate. Preferably, the nanowires are formed by the preferred methods for fabrication of Group III-V nanowires on silicon. Devices can be formed with core/shell and core/multi-shell nanowires and the devices are released from the substrate upon which the nanowires were formed to create a flexible structure that includes an array of vertical nanowires embedded in polymer.

Abstract translation: 本发明的实施例提供了一种在硅衬底上直接异质外延生长垂直III-V半导体纳米线的方法。 蚀刻硅衬底以基本上完​​全去除天然氧化物。 将其迅速置于反应室中。 将基底加热并保持在生长温度。 III-V族前体流过生长时间。 优选的实施例中，硅上的垂直III-V族III族纳米线具有核 - 壳结构，其提供径向同态结或异质结。 掺杂的纳米线芯由具有互补掺杂的壳包围。 这样可以由于在垂直的纳米线的轴向方向上的长的光路而提供高的光学吸收，同时在径向方向收集载体之前要大大减小载体必须扩散的距离。 合金成分也可以变化。 可以实现径向和轴向同态和异质结。 实施例提供柔性III-V族纳米线结构。 III-V族纳米线结构阵列嵌入聚合物中。 制造方法在衬底（例如，硅衬底）上形成垂直的纳米线。 优选地，通过在硅上制造III-V族III族纳米线的优选方法形成纳米线。 器件可以用核/壳和核/多壳纳米线形成，并且器件从其上形成纳米线的衬底释放以产生包括嵌入聚合物中的垂直纳米线阵列的柔性结构。

公开(公告)号：US07911012B2

公开(公告)日：2011-03-22

申请号：US12009581

申请日：2008-01-18

Applicant: Glenn Leedy

Inventor： Glenn Leedy

IPC: G01L9/00

CPC classification number: H01L25/50 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/942 ,  Y10S438/967 ,  Y10S438/977 ,  Y10T29/49128 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/4921 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/80001

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。

公开(公告)号：US07670893B2

公开(公告)日：2010-03-02

申请号：US10700429

申请日：2003-11-03

Applicant: Glenn J Leedy

Inventor： Glenn J Leedy

IPC: H01L21/8238 ,  H01L23/58

CPC classification number: H01L25/50 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/942 ,  Y10S438/967 ,  Y10S438/977 ,  Y10T29/49128 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/4921 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/80001

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。

公开(公告)号：US20080302559A1

公开(公告)日：2008-12-11

申请号：US12009581

申请日：2008-01-18

Applicant: Glenn Joseph Leedy

Inventor： Glenn Joseph Leedy

IPC: H05K1/00

CPC classification number: H01L25/50 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/942 ,  Y10S438/967 ,  Y10S438/977 ,  Y10T29/49128 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/4921 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/80001

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。

公开(公告)号：US20080118757A1

公开(公告)日：2008-05-22

申请号：US11979447

申请日：2007-11-02

Applicant: Shoji Akiyama ,  Yoshihiro Kubota ,  Atsuo Ito ,  Koichi Tanaka ,  Makoto Kawai ,  Yuuji Tobisaka

Inventor： Shoji Akiyama ,  Yoshihiro Kubota ,  Atsuo Ito ,  Koichi Tanaka ,  Makoto Kawai ,  Yuuji Tobisaka

IPC: B32B9/00 ,  B29C65/00

CPC classification number: H01L21/76254 ,  C30B29/06 ,  C30B33/00 ,  H01L21/2007 ,  H01L29/78603 ,  Y10S438/967 ,  Y10T428/31612

Abstract: Hydrogen ions are implanted to a surface (main surface) of the single crystal Si substrate 10 to form the hydrogen ion implanted layer (ion-implanted damage layer) 11. As a result of the hydrogen ion implantation, the hydrogen ion implanted boundary 12 is formed. The single crystal Si substrate 10 is bonded to the quartz substrate 20 having a carbon concentration of 100 ppm or higher, and an external shock is applied near the ion-implanted damage layer 11 to delaminate the Si crystal film along the hydrogen ion implanted boundary 12 of the single crystal Si substrate 10 out of the bonded substrate. Then, the surface of the resultant silicon thin film 13 is polished to remove a damaged portion, so that an SOQ substrate can be fabricated. There can be provided an SOQ substrate highly adaptable to a semiconductor device manufacturing process.

Abstract translation: 将氢离子注入单晶Si衬底10的表面（主表面），以形成氢离子注入层（离子注入损伤层）11。 作为氢离子注入的结果，形成氢离子注入边界12。 将单晶Si衬底10接合到碳浓度为100ppm以上的石英衬底20上，并且在离子注入损伤层11附近施加外部冲击，以沿着氢离子注入边界12剥离Si晶体膜 的单晶Si衬底10。 然后，对所得的硅薄膜13的表面进行抛光以去除损坏部分，从而可以制造出SOQ基板。 可以提供高度适应于半导体器件制造工艺的SOQ衬底。

公开(公告)号：US20060003555A1

公开(公告)日：2006-01-05

申请号：US10883887

申请日：2004-07-02

Applicant: Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

Inventor： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  C30B1/00 ,  H01L21/20 ,  H01L21/36

CPC classification number: H01L21/76259 ,  Y10S438/967

Abstract: A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

公开(公告)号：US06946369B2

公开(公告)日：2005-09-20

申请号：US10718109

申请日：2003-11-19

Applicant: Frédéric Mazen ,  Thierry Baron ,  Jean-Michel Hartmann ,  Marie-Noelle Semeria

Inventor： Frédéric Mazen ,  Thierry Baron ,  Jean-Michel Hartmann ,  Marie-Noelle Semeria

IPC: B82B3/00 ,  C23C16/04 ,  C30B25/00 ,  C30B25/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  C23C16/04 ,  C30B25/00 ,  C30B25/02 ,  C30B29/605 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/28273 ,  H01L29/0673 ,  Y10S438/967

Abstract: The invention concerns a method for forming nanostructures of semi-conductor material on a substrate of dielectric material by chemical vapour deposition (CVD). Said method comprises the following steps: a step of forming on the substrate (12) stable nuclei (14) of a first semi-conductor material in the form of islands, by CVD from a precursor (11) of the first semi-conductor material chosen so that the dielectric material (12) accepts the formation of said nuclei (14), a step of forming nanostructures (16A, 16B) of a second semi-conductor material from the stable nuclei (14) of the first semi-conductor material, by CVD from a precursor (21) chosen to generate a selective deposition of the second semi-conductor material only on said nuclei (14). The invention further concerns nanostructures formed according to one of said methods as well as devices comprising said nanostructures.

Abstract translation: 本发明涉及通过化学气相沉积（CVD）在介电材料的衬底上形成半导体材料的纳米结构的方法。 所述方法包括以下步骤：通过CVD从第一半导体材料的前体（11）在衬底（12）上形成岛状形式的第一半导体材料的稳定核（14）的步骤 选择使得介电材料（12）接受所述核（14）的形成;从第一半导体材料的稳定核（14）形成第二半导体材料的纳米结构（16A，16B）的步骤， 导体材料，通过CVD从前体（21）中选择以仅在所述核（14）上产生第二半导体材料的选择性沉积。 本发明还涉及根据所述方法之一形成的纳米结构以及包含所述纳米结构的器件。

公开(公告)号：US06933566B2

公开(公告)日：2005-08-23

申请号：US10059422

申请日：2002-01-31

Applicant: Nestor Alexander Bojarczuk, Jr. ,  Matthew Warren Copel ,  Supratik Guha ,  Vijay Narayanan

Inventor： Nestor Alexander Bojarczuk, Jr. ,  Matthew Warren Copel ,  Supratik Guha ,  Vijay Narayanan

IPC: H01L21/20 ,  H01L21/316 ,  H01L21/36 ,  H01L27/01 ,  H01L27/12

CPC classification number: H01L21/02488 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/31604 ,  H01L21/31691 ,  Y10S438/967

Abstract: A method (and resultant structure) of forming a semiconductor structure, includes processing an oxide to have a crystalline arrangement, and depositing an amorphous semiconductor layer on the oxide by one of evaporation and chemical vapor deposition (CVD).

Abstract translation: 形成半导体结构的方法（和结果）包括处理氧化物以具有结晶布置，以及通过蒸发和化学气相沉积（CVD）之一在氧化物上沉积非晶半导体层。

公开(公告)号：US20050156265A1

公开(公告)日：2005-07-21

申请号：US11042581

申请日：2005-01-24

Applicant: Glenn Leedy

Inventor： Glenn Leedy

IPC: G21K5/02 ,  B81B3/00 ,  G02F1/13 ,  G03F7/20 ,  G11C29/00 ,  H01L21/027 ,  H01L21/306 ,  H01L21/331 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/98 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L27/00 ,  H01L27/02 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/732 ,  H01L29/78 ,  H01L29/786 ,  H05G1/00 ,  G01R31/26 ,  H01L21/00 ,  H01L21/50

CPC classification number: H01L25/50 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/938 ,  Y10S438/942 ,  Y10S438/967 ,  Y10S438/977 ,  Y10T29/49128 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/4921 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/80001

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。