公开(公告)号：US5663093A

公开(公告)日：1997-09-02

申请号：US665328

申请日：1996-06-17

申请人： Horng-Huei Tseng ,  Chih-Yuan Lu

发明人： Horng-Huei Tseng ,  Chih-Yuan Lu

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for manufacturing a cylindrical stacked capacitor having a central spine for a DRAM using only one photo mask is provided. The invention uses sidewall spacers and selective etching techniques to form a low cost, simple to manufacture, high capacitance capacitor and DRAM cell. A substrate having source regions, drain regions and gate electrode structures is provided. An insulating layer with a contact opening is formed over the substrate surface. A first conductive layer and a first dielectric layer are formed over the insulating layer. The first dielectric layer and first conductive layer are etched forming a central spine over the contact opening. The etched first dielectric layer forms a dielectric cap over central spine. Dielectric spacers are formed on the sidewall of the central spine and the dielectric cap. The remaining portions of the first conductive layer are anisotropically etched using the dielectric spacers and the dielectric cap as a mask. Conductive spacers are formed on the sidewalls of the dielectric spacers. The dielectric cap and the dielectric spacers are selectively etched thereby forming a crown shaped storage node having a central spine. A capacitor dielectric layer and a top electrode are formed over the crown shaped storage node and the insulating layer forming a crown shaped capacitor.

摘要翻译： 提供一种制造具有仅使用一个光掩模的DRAM的具有中央脊的圆柱形堆叠电容器的方法。 本发明使用侧壁间隔物和选择性蚀刻技术来形成低成本，易于制造的高容量电容器和DRAM单元。 提供具有源极区，漏极区和栅电极结构的衬底。 在衬底表面上形成具有接触开口的绝缘层。 第一导电层和第一介电层形成在绝缘层上。 第一电介质层和第一导电层被蚀刻在接触开口上形成中心脊。 蚀刻的第一介电层在中心脊上形成电介质盖。 电介质隔离物形成在中心脊和绝缘帽的侧壁上。 使用电介质间隔物和电介质盖作为掩模对第一导电层的剩余部分进行各向异性蚀刻。 导电间隔物形成在电介质间隔物的侧壁上。 选择性地蚀刻电介质盖和介电间隔物，从而形成具有中心脊的冠形存储节点。 电容器电介质层和顶部电极形成在冠形存储节点之上，绝缘层形成冠状电容器。

公开(公告)号：US5631480A

公开(公告)日：1997-05-20

申请号：US494637

申请日：1995-06-23

申请人： Horng-Huei Tseng ,  Chih-Yuan Lu

发明人： Horng-Huei Tseng ,  Chih-Yuan Lu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L28/82 ,  H01L28/86

摘要： A method, and resultant structure, is described for fabricating a DRAM (Dynamic Random Access Memory) cell having a stack capacitor with a ladder storage node, connected to a MOS (Metal Oxide Semiconductor) transistor with source and drain regions, to form a DRAM cell. A bottom electrode is connected to and extends up from the source region of the transistor, and has a top surface with a central cavity, and side surfaces extending down from the top surface in a step-like manner. These step-like sides are formed by a repeated two-step process of removing a portion of the vertical walls of a photoresist mask and removing a portion of the top surface of a layer of polysilicon from which the bottom electrode is formed. There is a capacitor dielectric over the bottom electrode. A top electrode is formed over the capacitor dielectric.

摘要翻译： 描述了一种用于制造具有梯形存储节点的堆叠电容器的DRAM（动态随机存取存储器）单元，其连接到具有源极和漏极区域的MOS（金属氧化物半导体）晶体管，以形成DRAM 细胞。 底部电极连接到晶体管的源极区域并且从晶体管的源极区域向上延伸，并具有具有中心空腔的顶表面，并且侧表面以阶梯状方式从顶表面向下延伸。 通过重复的两步法除去光致抗蚀剂掩模的垂直壁的一部分并且去除形成底部电极的多晶硅层的顶表面的一部分，形成这些阶梯状侧。 底部电极上有一个电容电介质。 在电容器电介质上形成顶部电极。

公开(公告)号：US06262449B1

公开(公告)日：2001-07-17

申请号：US08709964

申请日：1996-09-09

申请人： Chih-Yuan Lu ,  Horng-Huei Tseng

发明人： Chih-Yuan Lu ,  Horng-Huei Tseng

IPC分类号： H01L27108

CPC分类号： H01L27/1085 ,  H01L27/10805 ,  H01L28/40

摘要： A method for manufacturing an array of stacked capacitor is described that utilizes the sidewall of the capacitor node contact to increase the capacitance on a dynamic random access memory (DRAM) cell. The area occupied by the stacked capacitor is also restricted to the area over the FET source/drain area, thereby providing for the further reduction of the cell size. The method using a single mask level to form node contact openings in a thick insulating layer over the source/drain areas used for the node contact. A doped polysilicon layer is deposited filling the node contact openings and conformally coating the substrate. The polysilicon layer is oxidized to the thick insulating layer but not in the node contact openings. The oxidized portion of the polysilicon layer and the thick insulating layer are removed concurrently in a wet etch leaving free standing pillar-shaped bottom electrodes that also serve as the node contacts. The array of pillar-shaped stacked capacitors are completed by forming a interelectrode dielectric layer on the bottom electrodes and then depositing and patterning another doped polysilicon to form the top electrodes.

摘要翻译： 描述了制造堆叠电容器阵列的方法，其利用电容器节点接触件的侧壁来增加动态随机存取存储器（DRAM）单元上的电容。 层叠电容器占据的面积也限于FET源极/漏极区域上的面积，从而进一步减小电池尺寸。 使用单个掩模级别的方法在用于节点接触的源极/漏极区域上的厚绝缘层中形成节点接触开口。 沉积掺杂的多晶硅层，填充节点接触开口并保形地涂覆衬底。 多晶硅层被氧化成厚的绝缘层，但不在节​​点接触开口中。 在湿蚀刻中同时去除多晶硅层的氧化部分和厚的绝缘层，留下也用作节点接触的独立的柱状底部电极。 柱状堆叠电容器的阵列通过在底部电极上形成电极间电介质层，然后沉积和构图另一个掺杂多晶硅以形成顶部电极来完成。

公开(公告)号：US5759894A

公开(公告)日：1998-06-02

申请号：US808338

申请日：1997-02-28

申请人： Horng-Huei Tseng ,  Chih-Yuan Lu

发明人： Horng-Huei Tseng ,  Chih-Yuan Lu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/92

摘要： A method for forming a DRAM capacitor using HSG-Si includes forming a dielectric layer over a substrate. A portion of the dielectric layer is removed to expose a contact area on the substrate. A polysilicon layer is then formed over the dielectric layer and in the first trench. Then, a hemispherical-grained silicon (HSG-Si) layer is formed on the polysilicon layer using an initial phase HSG-Si process, thereby forming a large number of silicon grains on the polysilicon layer. Next, nitrogen atoms are implanted into the polysilicon layer using the HSG-Si layer as a mask to form nitrogen regions in the polysilicon layer. The HSG-Si layer is then removed and the polysilicon layer is thermally oxidized. The nitrogen regions function as an anti-oxidation mask so that polysilicon-oxide regions are formed between the nitrogen regions in the polysilicon layer. Afterwards, an etching process is performed using the polysilicon-oxide regions as a mask so that the nitrogen regions and portions of the polysilicon layer beneath the nitrogen regions are removed. This etching step forms second trenches in the polysilicon layer between the polysilicon-oxide regions, which are subsequently removed. After removing the polysilicon-oxide regions, the polysilicon layer is patterned and etched to form a bottom electrode of the capacitor of the dynamic random access memory. The capacitor dielectric and the top electrode of the capacitor are then formed using conventional methods.

摘要翻译： 使用HSG-Si形成DRAM电容器的方法包括在衬底上形成电介质层。 去除介电层的一部分以露出衬底上的接触区域。 然后在电介质层上和第一沟槽中形成多晶硅层。 然后，使用初始相HSG-Si工艺在多晶硅层上形成半球状硅（HSG-Si）层，从而在多晶硅层上形成大量的硅晶粒。 接下来，使用HSG-Si层作为掩模将氮原子注入到多晶硅层中，以在多晶硅层中形成氮区。 然后去除HSG-Si层，并且多晶硅层被热氧化。 氮区域用作抗氧化掩模，使得在多晶硅层中的氮区域之间形成多晶氧化物区域。 然后，使用多晶硅氧化物区域作为掩模进行蚀刻处理，使得氮区域和氮区域下方的多晶硅层的部分被去除。 该蚀刻步骤在多晶硅层之间形成第二沟槽，该多晶硅层随后被去除。 在去除多晶硅氧化物区域之后，对多晶硅层进行图案化和蚀刻以形成动态随机存取存储器的电容器的底部电极。 然后使用常规方法形成电容器电介质和电容器的顶部电极。

公开(公告)号：US5552620A

公开(公告)日：1996-09-03

申请号：US428763

申请日：1995-04-24

申请人： Chih-Yuan Lu ,  Horng-Huei Tseng

发明人： Chih-Yuan Lu ,  Horng-Huei Tseng

IPC分类号： H01L27/108

CPC分类号： H01L27/10841 ,  Y10S257/90

摘要： There is shown a method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor. There is provided a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate. A pattern is formed of bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric and the field oxide isolation. A silicon nitride layer is formed over the doped polysilicon layer. Patterning and etching is done to the silicon nitride layer and doped polysilicon layer to form the opening for the capacitor node contact to the buried source/drain of the vertical field effect transistor (switching device for the storage signal) and establish said gate electrode in the hole and word line pattern over the field oxide insulator. A silicon oxide spacer is formed over the sidewalls of the silicon nitride and doped polysilicon layer. A capacitor is formed in and over the hole to complete the vertical DRAM cell.

摘要翻译： 示出了制造垂直DRAM单元的方法，其包括具有栅电极和源极/漏极元件的电场效应晶体管和电容器。 在硅衬底中提供了场氧化物隔离的图案，其中存在到硅衬底的开口图案。 图案由位线和具有位于每个到所述硅衬底的每个开口内的孔的线的图案形成，孔和位线的线彼此垂直，并且线在所述硅衬底的计划位置处交叉 垂直DRAM单元以与硅衬底的开口的图案形成。 在孔的表面上形成栅极电介质。 在孔内和上方形成掺杂多晶硅层，使其覆盖栅极电介质和场氧化物隔离。 在掺杂多晶硅层上形成氮化硅层。 对氮化硅层和掺杂多晶硅层进行图案化和蚀刻，以形成用于电容器节点接触到垂直场效应晶体管（用于存储信号的开关器件）的掩埋源极/漏极的开口，并在 孔和字线图形在场氧化物绝缘体上。 在氮化硅和掺杂多晶硅层的侧壁上形成氧化硅隔离物。 在孔内和上方形成电容器以完成垂直DRAM单元。

公开(公告)号：US5550077A

公开(公告)日：1996-08-27

申请号：US435203

申请日：1995-05-05

申请人： Horng-Huei Tseng ,  Chih-Yuan Lu

发明人： Horng-Huei Tseng ,  Chih-Yuan Lu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91

摘要： An efficient method for manufacturing a comb-type capacitor for use as part of a DRAM cell in a silicon integrated circuit is described. A three toothed comb is created by first forming a central pedestal of polysilicon, providing oxide spacers on the vertical sides of said pedestal, coating said spacers with an additional layer of polysilicon, and then etching away said spacers thereby creating the comb structure. In addition to the comb, the method of the present invention also leads to the formation of a projecting rim of polysilicon that runs around all four sides of the capacitor structure, thereby further increasing its effective surface beyond that due to the comb.

摘要翻译： 描述了一种用于制造用作硅集成电路中的DRAM单元的一部分的梳状电容器的有效方法。 通过首先形成多晶硅的中心基座，在所述基座的垂直侧上提供氧化物隔离物，用附加的多晶硅层涂覆所述间隔物，然后蚀刻所述间隔物从而形成梳状结构，从而产生三齿梳。 除了梳子之外，本发明的方法还导致在电容器结构的所有四个侧面上形成突出的多晶硅边缘，从而进一步增加其有效表面超过由于梳子的有效表面。

公开(公告)号：US5534457A

公开(公告)日：1996-07-09

申请号：US375783

申请日：1995-01-20

申请人： Horng-Huei Tseng ,  Chih-Yuan Lu

发明人： Horng-Huei Tseng ,  Chih-Yuan Lu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/60 ,  H01L28/86

摘要： A DRAM having a high capacitance stacked capacitor is fabricated by forming gate structures in the device areas and lines over field oxide areas on a substrate. A first insulating layer is formed and patterned to leave the source/drain structures open in the device areas where electrical contact is desired to the stacked capacitors. A bottom electrode of the capacitor is now formed by depositing and patterning a second polysilicon layer and a second insulating layer. Next the second polysilicon layer is laterally etched so that portions of the second polysilicon layer are etched out underneath from the second insulating layer. A third polysilicon layer is formed on the vertical sidewalls of the second polysilicon layer. A capacitor dielectric layer is deposited over the substrate surface and patterned so that portions remain covering the second and third polysilicon layers. A top electrode is formed over the capacitor dielectric layer.

摘要翻译： 通过在衬底上的场氧化物区域上的器件区域和线中形成栅极结构来制造具有高电容层叠电容器的DRAM。 第一绝缘层被形成并图案化以使得源极/漏极结构在需要电接触到堆叠的电容器的器件区域中断开。 电容器的底部电极现在通过沉积和构图第二多晶硅层和第二绝缘层而形成。 接下来，第二多晶硅层被横向蚀刻，使得第二多晶硅层的部分在第二绝缘层的下方被蚀刻掉。 在第二多晶硅层的垂直侧壁上形成第三多晶硅层。 电容器介电层沉积在衬底表面上并被图案化，使得部分保持覆盖第二和第三多晶硅层。 在电容器电介质层上形成顶部电极。

公开(公告)号：US5451537A

公开(公告)日：1995-09-19

申请号：US289633

申请日：1994-08-12

申请人： Horng-Huei Tseng ,  Chih-Yuan Lu

发明人： Horng-Huei Tseng ,  Chih-Yuan Lu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L28/82 ,  H01L28/86

摘要： A method, and resultant structure, is described for fabricating a DRAM (Dynamic Random Access Memory) cell having a stack capacitor with a ladder storage node, connected to a MOS (Metal Oxide Semiconductor) transistor with source and drain regions, to form a DRAM cell. A bottom electrode is connected to and extends up from the source region of the transistor, and has a top surface with a central cavity, and side surfaces extending down from the top surface in a step-like manner. These step-like sides are formed by a repeated two-step process of removing a portion of the vertical walls of a photoresist mask and removing a portion of the top surface of a layer of polysilicon from which the bottom electrode is formed. There is a capacitor dielectric over the bottom electrode. A top electrode is formed over the capacitor dielectric.

摘要翻译： 描述了一种用于制造具有梯形存储节点的堆叠电容器的DRAM（动态随机存取存储器）单元，其连接到具有源极和漏极区域的MOS（金属氧化物半导体）晶体管，以形成DRAM 细胞。 底部电极连接到晶体管的源极区域并且从晶体管的源极区域向上延伸，并具有具有中心空腔的顶表面，并且侧表面以阶梯状方式从顶表面向下延伸。 通过重复的两步法除去光致抗蚀剂掩模的垂直壁的一部分并且去除形成底部电极的多晶硅层的顶表面的一部分，形成这些阶梯状侧。 底部电极上有一个电容电介质。 在电容器电介质上形成顶部电极。

公开(公告)号：US5804480A

公开(公告)日：1998-09-08

申请号：US807441

申请日：1997-02-28

申请人： Chih-Yuan Lu ,  Horng-Huei Tseng

发明人： Chih-Yuan Lu ,  Horng-Huei Tseng

IPC分类号： H01L21/02 ,  H01L21/205 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L27/10817 ,  H01L28/92

摘要： A method for forming a DRAM capacitor using a HSG-Si includes forming a dielectric layer over a substrate. A polysilicon layer is formed over the dielectric layer, and a hemispherical-grained silicon (HSG-Si) layer is formed on the polysilicon layer using an initial phase HSG-Si process. The HSG-Si layer includes a large number of silicon grains spaced apart on the surface of the polysilicon layer with the area of the polysilicon layer's surface being left exposed. Next, oxygen is implanted into the polysilicon layer using the silicon grains as an implant mask, thereby forming oxygen regions in the polysilicon layer. The HSG-Si layer is removed and the oxygen regions are annealed to transform the atom regions into oxide regions. Afterwards, the polysilicon layer is etched using the oxide regions as an etching mask, thereby forming a large number of trenches in the polysilicon layer. The oxide regions and portions of the polysilicon layer are removed to form a storage node, which serves as a bottom electrode of the DRAM cell capacitor.

摘要翻译： 使用HSG-Si形成DRAM电容器的方法包括在衬底上形成电介质层。 在电介质层上形成多晶硅层，使用初始相HSG-Si工艺在多晶硅层上形成半球状硅（HSG-Si）层。 HSG-Si层包括在多晶硅层的表面上间隔开的多个硅颗粒，多晶硅层的表面的面积被暴露。 接下来，使用硅晶粒作为注入掩模将氧注入多晶硅层，从而在多晶硅层中形成氧区。 除去HSG-Si层，对氧区进行退火，将原子区域变换为氧化物区域。 之后，使用氧化物区域蚀刻多晶硅层作为蚀刻掩模，从而在多晶硅层中形成大量的沟槽。 去除氧化物区域和多晶硅层的部分以形成用作DRAM单元电容器的底部电极的存储节点。

公开(公告)号：US5652165A

公开(公告)日：1997-07-29

申请号：US661251

申请日：1996-06-10

申请人： Chih-Yuan Lu ,  Horng-Huei Tseng

发明人： Chih-Yuan Lu ,  Horng-Huei Tseng

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The present invention provides a method of manufacturing a stacked capacitor having a double walled crown shape. The method begins by providing a field effect transistor adjacent to a field oxide region in a substrate. Next, a first insulating layer and a barrier layer is formed over the resultant surface. A node contact opening is then etched in the barrier layer and the first insulation layer exposing a source region of the transistor. A first conductive layer is formed in the node contact opening and covers the first silicon nitride layer. A masking block is then formed over at least the node contact hole. First conductive spacers are then formed on the sidewalls of the masking block. Nitride spacers are formed on the sidewalls of the first conductive spacers. Second conductive spacers are formed on the sidewalls of the nitride spacers. The first conductive layer is anisotropically etched using the cylinder block, first conductive spacers, and the dielectric spacers as a mask. The masking block and the nitride spacers are removed thereby forming a double wall crown shape bottom electrode. A capacitor dielectric layer and top plate are formed to complete the capacitor.

摘要翻译： 本发明提供一种制造具有双层冠状的叠层电容器的方法。 该方法开始于提供与衬底中的场氧化物区域相邻的场效应晶体管。 接下来，在所得表面上形成第一绝缘层和阻挡层。 然后在阻挡层中蚀刻节点接触开口，并且第一绝缘层暴露晶体管的源极区域。 第一导电层形成在节点接触开口中并覆盖第一氮化硅层。 然后在至少节点接触孔上形成屏蔽块。 然后在掩模块的侧壁上形成第一导电间隔物。 氮化物间隔物形成在第一导电间隔物的侧壁上。 第二导电间隔物形成在氮化物间隔物的侧壁上。 使用气缸体，第一导电间隔件和电介质间隔件作为掩模对第一导电层进行各向异性蚀刻。 去除掩模块和氮化物间隔物，从而形成双壁冠形底部电极。 形成电容器电介质层和顶板以完成电容器。