公开(公告)号：US08314031B2

公开(公告)日：2012-11-20

申请号：US12726347

申请日：2010-03-18

Applicant: Chia-Lin Hsu

Inventor： Chia-Lin Hsu

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/3212

Abstract: A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening. A second CMP step is conducted using a second slurry to remove the metal hard mask.

Abstract translation: 描述了一种预镶嵌结构的平面化方法，其中预镶嵌结构包括设置在其中具有镶嵌开口的第一材料层上的金属硬掩模和填充镶嵌开口并覆盖金属的第二材料层 硬面膜 使用第一浆料进行第一CMP步骤以除去镶嵌开口外部的第二材料层。 使用第二浆料进行第二CMP步骤以除去金属硬掩模。

公开(公告)号：US20120264302A1

公开(公告)日：2012-10-18

申请号：US13085502

申请日：2011-04-13

Applicant: Chun-Wei Hsu ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Po-Cheng Huang ,  Chia-Hsi Chen ,  Yen-Ming Chen ,  Chih-Hsun Lin

Inventor： Chun-Wei Hsu ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Po-Cheng Huang ,  Chia-Hsi Chen ,  Yen-Ming Chen ,  Chih-Hsun Lin

IPC: H01L21/306

CPC classification number: H01L21/31053 ,  H01L21/02065 ,  H01L21/76224 ,  H01L29/66545

Abstract: A chemical mechanical polishing (CMP) process includes steps of providing a substrate, performing a first polishing step to the substrate with an acidic slurry, and performing a second polishing step to the substrate with a basic slurry after the first polishing step.

Abstract translation: 化学机械抛光（CMP）工艺包括以下步骤：提供基材，用酸性浆料对基材进行第一抛光步骤，以及在第一抛光步骤之后用碱性浆料对基材进行第二抛光步骤。

公开(公告)号：US07232752B2

公开(公告)日：2007-06-19

申请号：US10603924

申请日：2003-06-24

Applicant: Shao-Chung Hu ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yung-Tsung Wei

Inventor： Shao-Chung Hu ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yung-Tsung Wei

IPC: H01L21/4763 ,  H01L21/302

CPC classification number: H01L21/3212 ,  H01L21/02074

Abstract: A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.

Abstract translation: 化学机械抛光（CMP）后从硅晶片去除污染物的方法。 在铜化学机械抛光和随后的屏障化学 - 机械抛光操作之后，施加去离子水中的臭氧水溶液以清洁硅晶片，从而去除晶片上的污染物。 或者，在铜和阻挡CMP之后进行臭氧/去离子水缓冲抛光工艺，然后使用化学溶液或去离子水清洁晶片。 或者，在铜CMP和阻挡CMP两者之后进行臭氧/去离子水缓冲抛光工艺，然后使用化学溶液或去离子水清洁晶片。

公开(公告)号：US20070032077A1

公开(公告)日：2007-02-08

申请号：US11161530

申请日：2005-08-08

Applicant: Tzung-Yu Hung ,  Chien-Chung Huang ,  Chao-Ching Hsieh ,  Chia-Lin Hsu

Inventor： Tzung-Yu Hung ,  Chien-Chung Huang ,  Chao-Ching Hsieh ,  Chia-Lin Hsu

IPC: H01L21/44

CPC classification number: H01L21/76828 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883

Abstract: A method for manufacturing a metal plug is described. A substrate with an opening is provided. Then, a barrier layer is formed on a surface of the opening. Thereafter, a metallic layer is formed over the substrate so that the opening is also filled. Next, a planarization process is performed to remove the metallic layer outside the opening. One main feature of the present invention is the performance of at least a high temperature treatment after the metallic layer is formed. Due to the high temperature treatment, internal stress between different layers is released.

Abstract translation: 对金属插头的制造方法进行说明。 提供具有开口的基板。 然后，在开口的表面上形成阻挡层。 此后，在基板上形成金属层，使得开口也被填充。 接下来，进行平面化处理以去除开口外部的金属层。 本发明的一个主要特征是在形成金属层之后进行至少高温处理。 由于高温处理，不同层之间的内部应力被释放。

公开(公告)号：US20060211242A1

公开(公告)日：2006-09-21

申请号：US11308341

申请日：2006-03-17

Applicant: Chia-Lin Hsu ,  Chih-Chan Yu ,  Chien-Chung Huang

Inventor： Chia-Lin Hsu ,  Chih-Chan Yu ,  Chien-Chung Huang

IPC: H01L21/44

CPC classification number: H01L21/31053 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76883

Abstract: A method of forming a plug is provided. First, a substrate comprising at least a dielectric layer is provided, and a patterned hard mask is formed on the dielectric layer to define a position of at least a plug hole. Subsequently, the dielectric layer is etched for forming the plug hole. A barrier layer and a conductive layer are formed on the substrate, and the plug hole is filled by the conductive layer. Thereafter, first, second, and third chemical mechanical polishing processes are performed in turn. Finally, a fourth chemical mechanical polishing process is performed to remove portions of the conductive layer.

Abstract translation: 提供一种形成插头的方法。 首先，提供包括至少介电层的基板，并且在电介质层上形成图案化的硬掩模，以限定至少一个插塞孔的位置。 随后，蚀刻电介质层以形成插塞孔。 在基板上形成阻挡层和导电层，并且通过导电层填充插塞孔。 此后，依次执行第一，第二和第三化学机械抛光工艺。 最后，执行第四种化学机械抛光工艺以去除部分导电层。

公开(公告)号：US06797190B2

公开(公告)日：2004-09-28

申请号：US10383983

申请日：2003-03-06

Applicant: Chia-Lin Hsu ,  Art Yu ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

Inventor： Chia-Lin Hsu ,  Art Yu ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

IPC: B24D1100

CPC classification number: B24B37/30

Abstract: A wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same are provided. The present wafer carrier assembly comprises a first plate, a second plate and a flexible membrane. The first plate has a plurality of protrusions formed on a bottom surface thereof and the second plate has a plurality of apertures passing through. Each of the protrusions is matched with one of the apertures to enable the first plate and the second plate to detachably combine together. The flexible membrane is positioned under the second plate and contacts it. A surface of the flexible membrane opposite to the surface of the flexible membrane contacting the second plate provides a wafer-receiving surface.

Abstract translation: 提供了一种用于化学机械抛光装置的晶片载体组件和使用其的抛光方法。 本晶片载体组件包括第一板，第二板和柔性膜。 第一板具有在其底表面上形成的多个突起，并且第二板具有穿过的多个孔。 每个突起与其中一个孔匹配，以使得第一板和第二板能够可拆卸地组合在一起。 柔性膜定位在第二板下方并与其接触。 与柔性膜的与第二板接触的表面相对的柔性膜的表面提供了晶片接收表面。

公开(公告)号：US06638830B1

公开(公告)日：2003-10-28

申请号：US10065104

申请日：2002-09-18

Applicant: Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng

Inventor： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng

IPC: H01L2120

CPC classification number: H01L28/91 ,  H01L21/31604 ,  H01L21/3162 ,  H01L23/5223 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a high-density capacitor. At least one first trench is formed in a dielectric layer positioned on a semiconductor substrate. A first liner layer and a first conductive layer are formed on the semiconductor substrate followed by a first planarization process. At least one second trench having a joint side wall with the first trench is formed in the dielectric layer. A capacitor dielectric layer, a second liner layer, and a second conductive layer are formed on the semiconductor substrate followed by a second planarization process. The surfaces of the first conductive layer and the second conductive layer are then exposed to form a high-density capacitor having a three-dimensional structure.

Abstract translation: 一种制造高密度电容器的方法。 至少一个第一沟槽形成在位于半导体衬底上的电介质层中。 在半导体衬底上形成第一衬里层和第一导电层，接着进行第一平面化处理。 在电介质层中形成具有与第一沟槽的接合侧壁的至少一个第二沟槽。 在半导体衬底上形成电容器电介质层，第二衬垫层和第二导电层，接着进行第二平面化处理。 然后将第一导电层和第二导电层的表面暴露以形成具有三维结构的高密度电容器。

公开(公告)号：US06593185B1

公开(公告)日：2003-07-15

申请号：US10150385

申请日：2002-05-17

Applicant: Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng ,  Yi-Hsiung Lin

Inventor： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng ,  Yi-Hsiung Lin

IPC: H01L218242

CPC classification number: H01L27/108 ,  H01L28/90

Abstract: A method for fabricating a vertical three-dimensional metal-insulator-metal capacitor (MIM capacitor) structure is disclosed. The present invention utilized a vertical three-dimensional MIM capacitor structure on the substrate to decrease the structure area of the MIM capacitor in logic integrated circuit and integration for copper dual damascene process at an identical capacitance on a chip; therefore, the capacitance density of the vertical three-dimensional capacitor can be increased. Furthermore, the present invention is provided a method for fabricating the vertical three-dimensional MIM capacitor structure that compatible with the fabrication of the copper dual damascene structure such that the number of the photomask during the fabrication process can be reduced.

Abstract translation: 公开了一种用于制造垂直三维金属 - 绝缘体 - 金属电容器（MIM电容器）结构的方法。 本发明在衬底上利用垂直三维MIM电容器结构，以降低逻辑集成电路中MIM电容器的结构面积，并在芯片上的相同电容下对铜双镶嵌工艺进行集成; 因此，可以增加垂直三维电容器的电容密度。 此外，本发明提供一种制造与铜双镶嵌结构的制造兼容的垂直三维MIM电容器结构的方法，使得可以减少在制造过程中的光掩模的数量。