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    High voltage device with a parallel resistor
    5.
    发明授权
    High voltage device with a parallel resistor 有权
    具有并联电阻的高压器件

    公开(公告)号：US08624322B1

    公开(公告)日：2014-01-07

    申请号：US13551262

    申请日：2012-07-17

    申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Jen-Hao Yeh ,  Chun-Wei Hsu

    发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Jen-Hao Yeh ,  Chun-Wei Hsu

    IPC分类号： H01L23/62 ,  H01L21/8234

    CPC分类号： H01L27/0629

    摘要： Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.

    摘要翻译： 提供高压半导体器件。 高电压半导体器件包括具有栅极，源极和漏极的晶体管。 源极和漏极形成在掺杂衬底中并且由衬底的漂移区域分离。 栅极形成在漂移区域上以及源极和漏极之间。 晶体管被配置为处理至少几百伏特的高电压条件。 高电压半导体器件包括在晶体管的源极和漏极之间形成的电介质结构。 电介质结构突出进出基板。 电介质结构的不同部分具有不均匀的厚度。 高电压半导体器件包括在电介质结构上形成的电阻器。 电阻器具有大致均匀间隔开的多个绕组段。

    Poly opening polish process
    6.
    发明授权
    Poly opening polish process 有权
    多开口抛光工艺

    公开(公告)号：US08513128B2

    公开(公告)日：2013-08-20

    申请号：US13162776

    申请日：2011-06-17

    申请人： Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    发明人： Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    IPC分类号： H01L21/304 ,  H01L21/306 ,  B44C1/22

    CPC分类号： H01L21/31053 ,  H01L21/02065 ,  H01L29/517 ,  H01L29/66545

    摘要： A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

    摘要翻译： 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板，设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂，碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物，从而提高集成电路的性能，降低集成电路的生产成本。

    HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME
    7.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME 有权
    高电子移动性晶体管及其形成方法

    公开(公告)号：US20130105808A1

    公开(公告)日：2013-05-02

    申请号：US13297525

    申请日：2011-11-16

    申请人： King-Yuen WONG ,  Chen-Ju YU ,  Fu-Wei YAO ,  Chun-Wei HSU ,  Jiun-Lei Jerry YU ,  Chih-Wen HSIUNG ,  Fu-Chih YANG

    发明人： King-Yuen WONG ,  Chen-Ju YU ,  Fu-Wei YAO ,  Chun-Wei HSU ,  Jiun-Lei Jerry YU ,  Chih-Wen HSIUNG ,  Fu-Chih YANG

    IPC分类号： H01L29/20 ,  H01L21/335 ,  H01L29/778

    CPC分类号： H01L29/7786 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7787

    摘要： A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.

    摘要翻译： 半导体结构包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 载体通道位于第一III-V化合物层和第二III-V化合物层之间。 源特征和漏极特征设置在第二III-V复合层上。 栅电极设置在源特征和漏极特征之间的第二III-V化合物层之上。 在栅电极下方的第二III-V化合物层中嵌入有氟区。 栅介质层设置在第二III-V化合物层上。 栅极电介质层在氟区域上具有氟链段，并且在栅电极的至少一部分下方具有氟链段。

    SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
    8.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME 有权
    半导体结构及其形成方法

    公开(公告)号：US20130087804A1

    公开(公告)日：2013-04-11

    申请号：US13270502

    申请日：2011-10-11

    申请人： Fu-Wei YAO ,  Chun-Wei HSU ,  Chen-Ju YU ,  Jiun-Lei Jerry YU ,  Fu-Chih YANG ,  Chih-Wen HSIUNG

    发明人： Fu-Wei YAO ,  Chun-Wei HSU ,  Chen-Ju YU ,  Jiun-Lei Jerry YU ,  Fu-Chih YANG ,  Chih-Wen HSIUNG

    IPC分类号： H01L29/778 ,  H01L21/335 ,  H01L29/205

    CPC分类号： H01L21/0262 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

    摘要： A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A carrier channel depleting layer is disposed on the second III-V compound layer. The carrier channel depleting layer is deposited using plasma and a portion of the carrier channel depleting layer is under at least a portion of the gate electrode.

    摘要翻译： 半导体结构包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 载体通道位于第一III-V化合物层和第二III-V化合物层之间。 源特征和漏极特征设置在第二III-V复合层上。 栅电极设置在源特征和漏极特征之间的第二III-V化合物层之上。 载体通道耗尽层设置在第二III-V化合物层上。 使用等离子体沉积载流子通道耗尽层，并且载流子通道耗尽层的一部分位于栅电极的至少一部分之下。

    SEMICONDUCTOR PROCESS
    9.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号：US20130052825A1

    公开(公告)日：2013-02-28

    申请号：US13220692

    申请日：2011-08-30

    申请人： Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chun-Wei Hsu ,  Yen-Ming Chen ,  Chih-Hsun Lin ,  Chang-Hung Kung

    发明人： Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chun-Wei Hsu ,  Yen-Ming Chen ,  Chih-Hsun Lin ,  Chang-Hung Kung

    IPC分类号： H01L21/306

    CPC分类号： H01L21/3212 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/7684 ,  H01L21/823835 ,  H01L29/665

    摘要： A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.

    摘要翻译： 半导体工艺包括以下步骤。 第一栅极结构和第二栅极结构形成在基板上，其中第一栅极结构的顶部包括盖层，使得第一栅极结构的垂直高度高于第二栅极结构的垂直高度。 在基板上形成介电层。 执行第一化学机械抛光工艺以暴露盖层的顶表面。 执行第二化学机械抛光工艺以暴露第二栅极结构的顶表面，或执行蚀刻工艺以去除位于第二栅极结构上的介电层。 然后执行第二化学机械抛光工艺以除去盖层。

    System and method for communication security
    10.
    发明授权
    System and method for communication security 有权
    通信安全的系统和方法

    公开(公告)号：US08347369B2

    公开(公告)日：2013-01-01

    申请号：US12732212

    申请日：2010-03-26

    申请人： Chun-Wei Hsu

    发明人： Chun-Wei Hsu

    IPC分类号： G06F7/04

    CPC分类号： H04L63/123 ,  H04L63/083 ,  H04L63/20

    摘要： A system and method for communication security receives a request from a first communication device for communication with a second communication device, and determines if the communication is to be secure. The system and method further requests identity verification from the second communication device if the communication is to be secure. In addition, the system and method establishes a secure communication between the first communication device and the second communication device when a valid password is received from the second communication device.

    摘要翻译： 用于通信安全的系统和方法从第一通信设备接收与第二通信设备通信的请求，并确定通信是否安全。 如果通信是安全的，则系统和方法还请求来自第二通信设备的身份验证。 此外，当从第二通信设备接收到有效密码时，系统和方法建立第一通信设备和第二通信设备之间的安全通信。