公开(公告)号：US06797190B2

公开(公告)日：2004-09-28

申请号：US10383983

申请日：2003-03-06

申请人： Chia-Lin Hsu ,  Art Yu ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

发明人： Chia-Lin Hsu ,  Art Yu ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

IPC分类号： B24D1100

CPC分类号： B24B37/30

摘要： A wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same are provided. The present wafer carrier assembly comprises a first plate, a second plate and a flexible membrane. The first plate has a plurality of protrusions formed on a bottom surface thereof and the second plate has a plurality of apertures passing through. Each of the protrusions is matched with one of the apertures to enable the first plate and the second plate to detachably combine together. The flexible membrane is positioned under the second plate and contacts it. A surface of the flexible membrane opposite to the surface of the flexible membrane contacting the second plate provides a wafer-receiving surface.

摘要翻译： 提供了一种用于化学机械抛光装置的晶片载体组件和使用其的抛光方法。 本晶片载体组件包括第一板，第二板和柔性膜。 第一板具有在其底表面上形成的多个突起，并且第二板具有穿过的多个孔。 每个突起与其中一个孔匹配，以使得第一板和第二板能够可拆卸地组合在一起。 柔性膜定位在第二板下方并与其接触。 与柔性膜的与第二板接触的表面相对的柔性膜的表面提供了晶片接收表面。

公开(公告)号：US06638391B1

公开(公告)日：2003-10-28

申请号：US10177306

申请日：2002-06-19

申请人： Chia-Lin Hsu ,  Art Yu ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

发明人： Chia-Lin Hsu ,  Art Yu ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

IPC分类号： H01L21302

CPC分类号： B24B37/30

摘要： A wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same are provided. The present wafer carrier assembly comprises a first plate, a second plate and a flexible membrane. The first plate has a plurality of protrusions formed on a bottom surface thereof and the second plate has a plurality of apertures passing through. Each of the protrusions is matched with one of the apertures to enable the first plate and the second plate to detachably combine together. The flexible membrane is positioned under the second plate and contacts it. A surface of the flexible membrane opposite to the surface of the flexible membrane contacting the second plate provides a wafer-receiving surface.

摘要翻译： 提供了一种用于化学机械抛光装置的晶片载体组件和使用其的抛光方法。 本晶片载体组件包括第一板，第二板和柔性膜。 第一板具有在其底表面上形成的多个突起，并且第二板具有穿过的多个孔。 每个突起与其中一个孔匹配，以使得第一板和第二板能够可拆卸地组合在一起。 柔性膜定位在第二板下方并与其接触。 与柔性膜的与第二板接触的表面相对的柔性膜的表面提供了晶片接收表面。

公开(公告)号：US06660627B2

公开(公告)日：2003-12-09

申请号：US10063133

申请日：2002-03-25

申请人： Shao-Chung Hu ,  Hsueh-Chung Chen ,  Shih-Hsun Hsu ,  Chia-Lin Hsu

发明人： Shao-Chung Hu ,  Hsueh-Chung Chen ,  Shih-Hsun Hsu ,  Chia-Lin Hsu

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/31051

摘要： A method for planarization of a semiconductor wafer with a high selectivity is describe. The semiconductor wafer has a hard mask, a stop layer disposed on the hard mask, and a barrier layer disposed on the stop layer. The method includes performing a chemical mechanical polishing (CMP) process on the barrier layer so as to expose the stop layer, and removing the stop layer. The polishing selectivity of the barrier layer relative to the stop layer is greater than 50. Since the material of stop layer is different from the material of barrier layer, the high selectivity is easily achieved. Thus, the surface of semiconductor wafer can be highly planarized.

摘要翻译： 描述了一种以高选择性平坦化半导体晶片的方法。 半导体晶片具有硬掩模，设置在硬掩模上的阻挡层和设置在阻挡层上的阻挡层。 该方法包括在阻挡层上进行化学机械抛光（CMP）处理，以露出停止层，并除去停止层。 阻挡层相对于停止层的抛光选择性大于50.由于阻挡层的材料与阻挡层的材料不同，因此容易实现高选择性。 因此，半导体晶片的表面可以被高度平坦化。

公开(公告)号：US06709544B2

公开(公告)日：2004-03-23

申请号：US10064526

申请日：2002-07-24

申请人： Shao-Chung Hu ,  Chia-Lin Hsu ,  Hsueh-Chung Chen ,  Shih-Hsun Hsu

发明人： Shao-Chung Hu ,  Chia-Lin Hsu ,  Hsueh-Chung Chen ,  Shih-Hsun Hsu

IPC分类号： B24B700

CPC分类号： B24B37/20 ,  B24B37/042

摘要： The present invention related to a CMP equipment, compatible with the existing manufacture processes. The CMP equipment of the present invention employs strip polishing platens that can be smaller than the wafer size, so that the layout is compact and the space is effectively utilized, leading to high throughput and efficient production management. The present invention provides a CMP equipment that offers greater flexibility in performing CMP for different fabrication processes through the choices of various polishing pads and/or polishing slurry.

摘要翻译： 本发明涉及与现有制造工艺兼容的CMP设备。 本发明的CMP设备采用可以比晶片尺寸小的带状抛光压板，使得布局紧凑并且有效地利用空间，导致高产量和高效的生产管理。 本发明提供一种CMP设备，其通过选择各种抛光垫和/或抛光浆料，为不同的制造工艺执行CMP提供更大的灵活性。

公开(公告)号：US07714443B2

公开(公告)日：2010-05-11

申请号：US11458501

申请日：2006-07-19

申请人： Hsien-Wei Chen ,  Anbiarshy Wu ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Anbiarshy Wu ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

IPC分类号： H01L23/52

CPC分类号： H01L21/76895 ,  H01L22/34 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/30105

摘要： An interconnect structure includes at least a first interconnect layer and a second interconnect layer. Each of the first and second interconnect layers has a pad structure and each pad structure has a respective pad density. The pad density of the pad structure of the second interconnect layer is different from the pad density of the pad structure of the first interconnect layer. The pad structures of the first and second interconnect layers are connected to each other.

摘要翻译： 互连结构至少包括第一互连层和第二互连层。 第一和第二互连层中的每一个具有焊盘结构，并且每个焊盘结构具有相应的焊盘密度。 第二互连层的焊盘结构的焊盘密度不同于第一互连层的焊盘结构的焊盘密度。 第一和第二互连层的焊盘结构彼此连接。

公开(公告)号：US20070015365A1

公开(公告)日：2007-01-18

申请号：US11181433

申请日：2005-07-14

申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen ,  Shin-Puu Jeng ,  Jian-Hong Lin ,  Chih-Tao Lin ,  Shih-Hsun Hsu

发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen ,  Shin-Puu Jeng ,  Jian-Hong Lin ,  Chih-Tao Lin ,  Shih-Hsun Hsu

IPC分类号： H01L21/461

CPC分类号： H01L21/3212 ,  H01L21/31053

摘要： In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.

公开(公告)号：US20090200549A1

公开(公告)日：2009-08-13

申请号：US12426995

申请日：2009-04-21

申请人： Hsien-Wei Chen ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

发明人： Hsien-Wei Chen ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

IPC分类号： H01L23/00

CPC分类号： H01L23/585 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer.

摘要翻译： 公开了一种半导体器件。 该器件包括衬底和覆盖衬底的第一布线层。 第一布线层包括由第一密封环包围的第一布线区域。 第一密封环包括由嵌入在第一密封环中的第一介电层隔离的第一监测电路。 第一监视器电路响应于在第三电介质层中发生预定量的变形。

公开(公告)号：US20080296570A1

公开(公告)日：2008-12-04

申请号：US11754394

申请日：2007-05-29

申请人： Hsien-Wei Chen ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

发明人： Hsien-Wei Chen ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

IPC分类号： H01L23/58

CPC分类号： H01L23/585 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer.

摘要翻译： 公开了一种半导体器件。 该器件包括衬底和覆盖衬底的第一布线层。 第一布线层包括由第一密封环包围的第一布线区域。 第一密封环包括由嵌入在第一密封环中的第一介电层隔离的第一监测电路。 第一监视器电路响应于在第三电介质层中发生预定量的变形。

公开(公告)号：US07538346B2

公开(公告)日：2009-05-26

申请号：US11754394

申请日：2007-05-29

申请人： Hsien-Wei Chen ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

发明人： Hsien-Wei Chen ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

IPC分类号： H01L23/58

CPC分类号： H01L23/585 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer.

摘要翻译： 公开了一种半导体器件。 该器件包括衬底和覆盖衬底的第一布线层。 第一布线层包括由第一密封环包围的第一布线区域。 第一密封环包括由嵌入在第一密封环中的第一介电层隔离的第一监测电路。 第一监视器电路响应于在第三电介质层中发生预定量的变形。

公开(公告)号：US07235424B2

公开(公告)日：2007-06-26

申请号：US11181433

申请日：2005-07-14

申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen ,  Shin-Puu Jeng ,  Jian-Hong Lin ,  Chih-Tao Lin ,  Shih-Hsun Hsu

发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen ,  Shin-Puu Jeng ,  Jian-Hong Lin ,  Chih-Tao Lin ,  Shih-Hsun Hsu

IPC分类号： H01L21/00

CPC分类号： H01L21/3212 ,  H01L21/31053

摘要： In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.

摘要翻译： 在一个实施例中，本发明涉及一种用于在金属层的稀疏填充部分中插入虚拟图案的方法和装置。 虚拟图案反映了可能导致不均匀的后抛光膜厚度的半导体布局中的图案密度变化的影响。 根据本公开的一个实施例的算法基于金属层中的图案来确定虚拟图案的尺寸和位置，首先以小的虚拟图案围绕金属结构，然后用大的虚拟图案填充任何剩余的空隙。