Poly opening polish process
    3.
    发明授权
    Poly opening polish process 有权
    多开口抛光工艺

    公开(公告)号:US08513128B2

    公开(公告)日:2013-08-20

    申请号:US13162776

    申请日:2011-06-17

    CPC classification number: H01L21/31053 H01L21/02065 H01L29/517 H01L29/66545

    Abstract: A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

    Abstract translation: 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板,设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂,碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物,从而提高集成电路的性能,降低集成电路的生产成本。

    SEMICONDUCTOR PROCESS
    4.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号:US20130052825A1

    公开(公告)日:2013-02-28

    申请号:US13220692

    申请日:2011-08-30

    Abstract: A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.

    Abstract translation: 半导体工艺包括以下步骤。 第一栅极结构和第二栅极结构形成在基板上,其中第一栅极结构的顶部包括盖层,使得第一栅极结构的垂直高度高于第二栅极结构的垂直高度。 在基板上形成介电层。 执行第一化学机械抛光工艺以暴露盖层的顶表面。 执行第二化学机械抛光工艺以暴露第二栅极结构的顶表面,或执行蚀刻工艺以去除位于第二栅极结构上的介电层。 然后执行第二化学机械抛光工艺以除去盖层。

    PLANARIZATION PROCESS FOR PRE-DAMASCENE STRUCTURE INCLUDING METAL HARD MASK
    5.
    发明申请
    PLANARIZATION PROCESS FOR PRE-DAMASCENE STRUCTURE INCLUDING METAL HARD MASK 有权
    包括金属硬掩模的预结晶结构的平面化方法

    公开(公告)号:US20060286805A1

    公开(公告)日:2006-12-21

    申请号:US11160262

    申请日:2005-06-16

    Applicant: Chia-Lin Hsu

    Inventor: Chia-Lin Hsu

    CPC classification number: H01L21/3212

    Abstract: A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening. A second CMP step is conducted using a second slurry to remove the metal hard mask.

    Abstract translation: 描述了一种预镶嵌结构的平面化方法,其中预镶嵌结构包括设置在其中具有镶嵌开口的第一材料层上的金属硬掩模和填充镶嵌开口并覆盖金属的第二材料层 硬面膜 使用第一浆料进行第一CMP步骤以除去镶嵌开口外部的第二材料层。 使用第二浆料进行第二CMP步骤以除去金属硬掩模。

    METHOD OF FORMING BARRIER LAYER AND METHOD OF FABRICATING INTERCONNECT
    6.
    发明申请
    METHOD OF FORMING BARRIER LAYER AND METHOD OF FABRICATING INTERCONNECT 审中-公开
    形成障碍层的方法和制作互连的方法

    公开(公告)号:US20060128146A1

    公开(公告)日:2006-06-15

    申请号:US11163435

    申请日:2005-10-19

    CPC classification number: H01L21/2855 H01L21/76843

    Abstract: A method of fabricating a barrier layer is described. A material layer having an opening formed therein is provided. Then, the material layer is disposed inside a physical vapor deposition chamber and a first deposition process is performed to form a first barrier layer on the surface of the opening. The first deposition process includes turning on a plasma source and turning off the plasma source. The turning on of the plasma source and the turning off of the plasma source are separated from each other by an interval less than 2 seconds. Thereafter, the first deposition process is repeated several times to form a second barrier layer comprising a plurality of first barrier layers.

    Abstract translation: 描述制造阻挡层的方法。 提供其中形成有开口的材料层。 然后,将材料层设置在物理气相沉积室内部,并执行第一沉积工艺以在开口的表面上形成第一阻挡层。 第一沉积工艺包括打开等离子体源并关闭等离子体源。 等离子体源的导通和等离子体源的关闭彼此间隔小于2秒的间隔。 此后,重复多次第一沉积工艺以形成包括多个第一阻挡层的第二阻挡层。

    CHEMICAL MECHANICAL POLISHING PROCESS
    7.
    发明申请
    CHEMICAL MECHANICAL POLISHING PROCESS 有权
    化学机械抛光工艺

    公开(公告)号:US20060057944A1

    公开(公告)日:2006-03-16

    申请号:US10711392

    申请日:2004-09-16

    CPC classification number: H01L21/7684 C09G1/02 H01L21/3212 H01L21/76843

    Abstract: A high throughput chemical mechanical polishing process is disclosed. A substrate having thereon a top bulk metal layer and a lower barrier layer is prepared. The top bulk metal layer is polished at a substantial constant removal rate to expose the barrier layer by utilizing a first platen and first slurry being selective to the barrier layer. The exposed barrier layer is then polished by using a second platen and second slurry. The first slurry has a copper to barrier polishing selectivity of greater than 30.

    Abstract translation: 公开了高通量化学机械抛光工艺。 制备其上具有顶部本体金属层和下部阻挡层的基板。 顶部本体金属层以基本恒定的去除速率被抛光,以通过利用第一压板和对阻挡层有选择性的第一浆料来暴露阻挡层。 然后通过使用第二压板和第二浆料来抛光暴露的阻挡层。 第一种浆料具有大于30的铜屏障抛光选择性。

    Method of forming a dual damascene via by using a metal hard mask layer
    8.
    发明授权
    Method of forming a dual damascene via by using a metal hard mask layer 有权
    通过使用金属硬掩模层形成双镶嵌过孔的方法

    公开(公告)号:US06831013B2

    公开(公告)日:2004-12-14

    申请号:US09986929

    申请日:2001-11-13

    Abstract: This invention relates to a method of forming a dual damascene via, in particular to a method of forming a dual damascene via by using a metal hard mask layer. The present invention uses a metal layer to be a hard mask layer to make the surface of the isolation layer become a level and smooth surface and not become a rounding convex and to prevent the via being connected with others vias to cause the leakage defects after forming the shape of the via.

    Abstract translation: 本发明涉及一种形成双镶嵌层的方法,特别涉及通过使用金属硬掩模层形成双镶嵌过孔的方法。 本发明使用金属层作为硬掩模层,使得隔离层的表面变得水平和光滑的表面,并且不变成圆形凸起,并且防止通孔与其它通孔连接,以在成形之后引起泄漏缺陷 通孔的形状。

    Post-CMP removal of surface contaminants from silicon wafer
    9.
    发明授权
    Post-CMP removal of surface contaminants from silicon wafer 有权
    CMP后移除表面污染物

    公开(公告)号:US06696361B2

    公开(公告)日:2004-02-24

    申请号:US09854006

    申请日:2001-05-10

    CPC classification number: H01L21/02074 H01L21/3212

    Abstract: A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.

    Abstract translation: 化学机械抛光(CMP)后从硅晶片去除污染物的方法。 在铜化学机械抛光和随后的屏障化学 - 机械抛光操作之后,施加去离子水中的臭氧水溶液以清洁硅晶片,从而去除晶片上的污染物。 或者,在铜和阻挡CMP之后进行臭氧/去离子水缓冲抛光工艺,然后使用化学溶液或去离子水清洁晶片。 或者,在铜CMP和阻挡CMP两者之后进行臭氧/去离子水缓冲抛光工艺,然后使用化学溶液或去离子水清洁晶片。

    Chemical mechanical polishing method for copper

    公开(公告)号:US06616510B2

    公开(公告)日:2003-09-09

    申请号:US09735323

    申请日:2000-12-12

    CPC classification number: H01L21/3212 B24B37/044 C09G1/02

    Abstract: A chemical-mechanical polishing method for polishing a copper oxide layer and a copper layer. The copper oxide layer above the copper layer is first polished using an aqueous solution having a high concentration of polishing particles/chelating agent. The copper layer is then polished using a polishing slurry having a low concentration of polishing particles/chelating agent or the polishing slurry free of polishing particles/chelating agent. Alternatively, the copper oxide layer is polished using a mixture of the aqueous solution and the polishing slurry. After the copper oxide layer is removed, the copper layer is polished using the polishing slurry alone.

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