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    Apparatus with equalizing voltage generation circuit and methods of use
    51.
    发明申请
    Apparatus with equalizing voltage generation circuit and methods of use 有权
    具有均衡电压产生电路和使用方法的装置

    公开(公告)号：US20060126405A1

    公开(公告)日：2006-06-15

    申请号：US11347961

    申请日：2006-02-06

    申请人： Chulmin Jung

    发明人： Chulmin Jung

    IPC分类号： G11C7/06

    CPC分类号： G11C11/4094

    摘要： A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first voltage, which may be used as an equalization voltage for pairs of complementary digit lines. The oscillator is controlled by an oscillator control signal, which is produced by a feedback and control loop of the equalization voltage generator. The feedback and control loop includes a reference generator circuit to produce a stable, internal reference signal that is clamped at a maximum reference voltage. A comparator of the feedback and control loop compares the internal reference signal with a second voltage, which is proportional to the first voltage. The comparator causes the oscillator to turn on when the second voltage is lower than the reference voltage, and causes the oscillator to turn off when the second voltage is higher than the reference voltage.

    摘要翻译： 存储器件包括均衡电压发生器。 均衡电压发生器包括振荡器和电荷泵以产生第一电压，其可以用作互补数字线对的均衡电压。 振荡器由均衡电压发生器的反馈和控制回路产生的振荡器控制信号控制。 反馈和控制回路包括参考发生器电路，以产生稳定的内部参考信号，其被钳位在最大参考电压。 反馈和控制环路的比较器将内部参考信号与第一电压成比例的第二电压进行比较。 当第二电压低于参考电压时，比较器使振荡器导通，并且当第二电压高于参考电压时使振荡器关断。

    Memory Array Having Word Lines with Folded Architecture
    52.
    发明申请
    Memory Array Having Word Lines with Folded Architecture 有权
    具有折叠架构的字线的内存阵列

    公开(公告)号：US20130044550A1

    公开(公告)日：2013-02-21

    申请号：US13213019

    申请日：2011-08-18

    申请人： Chulmin Jung ,  Myron Buer

    发明人： Chulmin Jung ,  Myron Buer

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1012 ,  G11C5/025 ,  G11C8/14 ,  G11C11/4085 ,  G11C11/4087

    摘要： According to an exemplary embodiment, a memory array arrangement includes a plurality of word lines, where at least two of the plurality of word lines are concurrently active word lines. Each of the plurality of word lines drive at least one group of columns. The memory array arrangement also includes a multiplexer for coupling one memory cell in a selected group of columns to at least one of the plurality of sense amps, thereby achieving a reduced sense amp-to-column ratio. The memory array arrangement further includes a plurality of I/O buffers each corresponding to the at least one of the plurality of sense amps. The memory array arrangement thereby results in the plurality of word lines having reduced resistive and capacitive loading.

    摘要翻译： 根据示例性实施例，存储器阵列布置包括多个字线，其中多条字线中的至少两条字线是同时有效的字线。 多个字线中的每一个驱动至少一组列。 存储器阵列布置还包括多路复用器，用于将所选择的列组中的一个存储器单元耦合到多个感测放大器中的至少一个，从而实现减小的读出放大比率。 存储器阵列布置还包括多个I / O缓冲器，每个I / O缓冲器对应于多个感测放大器中的至少一个。 因此，存储器阵列布置导致多个字线具有降低的电阻和电容负载。

    Power saving sensing scheme for solid state memory
    54.
    发明授权
    Power saving sensing scheme for solid state memory 有权
    固态存储器的省电感测方案

    公开(公告)号：US07961526B2

    公开(公告)日：2011-06-14

    申请号：US12502932

    申请日：2009-07-14

    申请人： Chulmin Jung ,  Kang Yong Kim

    发明人： Chulmin Jung ,  Kang Yong Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C8/12 ,  G11C7/103 ,  G11C8/18

    摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.

    摘要翻译： 公开了诸如涉及固态存储器件的方法和装置。 一种这样的方法包括选择存储器阵列中的多个存储器单元。 确定存储在所选择的多个存储单元中的多个数据位的状态。 在确定多个数据位的状态时，多个数据位的一部分被感测得比其他数据位更快。 顺序提供多个数据位作为输出。 在一个实施例中，多个数据位的部分包括存储器件的顺序输出的第一位。

    Array sense amplifiers, memory devices and systems including same, and methods of operation
    55.
    发明申请
    Array sense amplifiers, memory devices and systems including same, and methods of operation 有权
    阵列读出放大器，包括其的存储器件和系统以及操作方法

    公开(公告)号：US20080159035A1

    公开(公告)日：2008-07-03

    申请号：US11646735

    申请日：2006-12-27

    申请人： Chulmin Jung ,  Tae Kim

    发明人： Chulmin Jung ,  Tae Kim

    IPC分类号： G11C7/10 ,  G11C7/06

    CPC分类号： G11C7/065 ,  G11C11/4091

    摘要： A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. The first amplifier stage, having a first conductivity-type, amplifies one of the I/O node towards a first voltage. The second amplifier stage, having a second conductivity-type, amplifies the other I/O node towards a second voltage. The sense amplifier also includes a resistance circuit coupled to the second amplifier stage to reduce the gain of the second amplifier stage thereby reducing the rate of amplification of the signal on the corresponding I/O node.

    摘要翻译： 描述了具有减小的增益的放大器级的读出放大器。 读出放大器包括第一输入/输出（“I / O”）节点和第二互补I / O节点。 读出放大器包括两个放大器级，每个用于放大I / O节点之一上的信号。 具有第一导电类型的第一放大器级将第一电压的I / O节点之一放大。 具有第二导电类型的第二放大器级将第二电压放大到另一个I / O节点。 读出放大器还包括耦合到第二放大器级的电阻电路，以减小第二放大器级的增益，从而降低相应I / O节点上的信号的放大率。

    Data path having grounded precharge operation and test compression capability
    56.
    发明授权
    Data path having grounded precharge operation and test compression capability 有权
    具有接地预充电操作和测试压缩能力的数据通路

    公开(公告)号：US07061817B2

    公开(公告)日：2006-06-13

    申请号：US10883619

    申请日：2004-06-30

    申请人： George Raad ,  Chulmin Jung

    发明人： George Raad ,  Chulmin Jung

    IPC分类号： G11C29/00

    CPC分类号： G11C29/40 ,  G11C2029/1204

    摘要： A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.

    摘要翻译： 用于在存储器单元和输入/输出（IO）线路读出放大器之间耦合数据的数据路径。 IO线耦合电路耦合到一对全局数据线和一对本地数据线，以根据用于存储器的本地数据线的电压电平将每个全局数据线耦合到电压源和从电压源分离 读操作。 对于存储器写入操作，IO线耦合电路将每个全局数据线耦合到每个本地数据线的相应的一个。 数据路径还包括耦合到全局数据线的第一预充电电路，以将全局数据线耦合到地，以在存储器读或写操作之前对信号线进行预充电，并且还可以包括耦合到全局数据的测试压缩电路 线条。

    Data path having grounded precharge operation and test compression capability
    57.
    发明申请
    Data path having grounded precharge operation and test compression capability 有权

    公开(公告)号：US20060002206A1

    公开(公告)日：2006-01-05

    申请号：US10883619

    申请日：2004-06-30

    申请人： George Raad ,  Chulmin Jung

    发明人： George Raad ,  Chulmin Jung

    IPC分类号： G11C29/00

    CPC分类号： G11C29/40 ,  G11C2029/1204

    摘要： A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.

    Memory array having word lines with folded architecture
    58.
    发明授权
    Memory array having word lines with folded architecture 有权
    具有折叠结构的字线的存储器阵列

    公开(公告)号：US08659955B2

    公开(公告)日：2014-02-25

    申请号：US13213019

    申请日：2011-08-18

    申请人： Chulmin Jung ,  Myron Buer

    发明人： Chulmin Jung ,  Myron Buer

    IPC分类号： G11C7/00 ,  G11C7/10

    CPC分类号： G11C7/1012 ,  G11C5/025 ,  G11C8/14 ,  G11C11/4085 ,  G11C11/4087

    摘要： According to an exemplary embodiment, a memory array arrangement includes a plurality of word lines, where at least two of the plurality of word lines are concurrently active word lines. Each of the plurality of word lines drive at least one group of columns. The memory array arrangement also includes a multiplexer for coupling one memory cell in a selected group of columns to at least one of the plurality of sense amps, thereby achieving a reduced sense amp-to-column ratio. The memory array arrangement further includes a plurality of I/O buffers each corresponding to the at least one of the plurality of sense amps. The memory array arrangement thereby results in the plurality of word lines having reduced resistive and capacitive loading.

    摘要翻译： 根据示例性实施例，存储器阵列布置包括多个字线，其中多条字线中的至少两条字线是同时有效的字线。 多个字线中的每一个驱动至少一组列。 存储器阵列布置还包括多路复用器，用于将所选择的列组中的一个存储器单元耦合到多个感测放大器中的至少一个，从而实现减小的读出放大比率。 存储器阵列布置还包括多个I / O缓冲器，每个I / O缓冲器对应于多个感测放大器中的至少一个。 因此，存储器阵列布置导致多个字线具有降低的电阻和电容负载。