公开(公告)号：US08406031B2

公开(公告)日：2013-03-26

申请号：US12970416

申请日：2010-12-16

申请人： Myron Buer ,  Dechang Sun ,  Duane Jacobson ,  David William Knebelsberger ,  Jan LeClair

发明人： Myron Buer ,  Dechang Sun ,  Duane Jacobson ,  David William Knebelsberger ,  Kevin LeClair

IPC分类号： G11C17/08

CPC分类号： G11C17/08 ,  G11C8/10 ,  G11C11/5692 ,  G11C17/12

摘要： Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.

摘要翻译： 实施例提供改进的存储器位单元，存储器阵列和存储器架构。 在一个实施例中，存储单元包括具有漏极，源极和栅极端子的晶体管; 以及多个节目节点，其中每个节目节点充电到预定电压并且耦合到多个位线中的相应一个位线。

公开(公告)号：US20100014340A1

公开(公告)日：2010-01-21

申请号：US12568430

申请日：2009-09-28

申请人： Myron Buer ,  Jonathan Schmitt ,  Laurentiu Vasiliu

发明人： Myron Buer ,  Jonathan Schmitt ,  Laurentiu Vasiliu

IPC分类号： G11C17/00 ,  G11C17/16

CPC分类号： G11C17/18 ,  G11C11/419 ,  G11C17/146 ,  G11C17/16

摘要： A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.

摘要翻译： 提供基于差分锁存器的一次可编程存储器单元。 基于差分锁存器的一次性可编程存储器单元包括差分锁存放大器，其具有耦合到第一输入端的第一组熔丝器件和耦合到第二输入端的第二组熔丝器件。 只能在存储单元中编写一组熔丝器件。 如果一组熔丝器件中的一个或多个保险丝器件被编程，则具有编程保险丝的一侧将在其对差分锁存放大器的输入端呈现较低的电压。 差分锁存放大器根据编程保险丝的一侧输出“0”或“1”。

公开(公告)号：US07649798B2

公开(公告)日：2010-01-19

申请号：US11505744

申请日：2006-08-17

申请人： Jonathan Alois Schmitt ,  Laurentiu Vasiliu ,  Myron Buer

发明人： Jonathan Alois Schmitt ,  Laurentiu Vasiliu ,  Myron Buer

IPC分类号： G11C7/00

CPC分类号： G11C17/18 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory.

摘要翻译： 这里描述了在集成电路中实现一个或多个天然NMOS反熔丝的方法。 还描述了一种用于编程在存储器件内使用的一个或多个天然NMOS反熔丝的方法。 该方法还包括在执行编程之后验证一个或多个天然NMOS反熔丝的一个或多个状态。 在代表性的实施例中，通过阻挡将掺杂剂注入集成电路的衬底来实现一个或多个天然NMOS反熔丝。 在代表性的实施例中，集成电路结合使用一个或多个天然NMOS反熔丝。 在代表性的实施例中，集成电路包括诸如一次性可编程存储器之类的存储器件。

公开(公告)号：US07136303B2

公开(公告)日：2006-11-14

申请号：US10929609

申请日：2004-08-31

申请人： Douglas D. Smith ,  Myron Buer ,  Bassem F. Radieddine

发明人： Douglas D. Smith ,  Myron Buer ,  Bassem F. Radieddine

IPC分类号： G11C11/34

CPC分类号： G11C17/16

摘要： A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based one-time programmable (OTP) element. In one example, the static storage element includes a thin gate-oxide that acts as a resistance element, which, depending on whether its blown, sets the latch into one of two states.

摘要翻译： 一次性可编程设备包括控制器，保护系统，静态存储元件和锁存器，其可被称为基于锁存器的一次可编程（OTP）元件。 在一个示例中，静态存储元件包括用作电阻元件的薄栅极氧化物，其根据其是否被熔断将锁存器设置为两种状态之一。

公开(公告)号：US20060044861A1

公开(公告)日：2006-03-02

申请号：US10929609

申请日：2004-08-31

申请人： Douglas Smith ,  Myron Buer ,  Bassem Radieddine

发明人： Douglas Smith ,  Myron Buer ,  Bassem Radieddine

IPC分类号： G11C17/00

CPC分类号： G11C17/16

摘要： A one-time programmable device includes a controller, a protection system, a static storage element and a latch, which can be referred to as a latch-based one-time programmable (OTP) element. In one example, the static storage element comprises a thin gate-oxide that acts as a resistance element, which, depending on whether its blown, sets the latch into one of two states.

摘要翻译： 一次性可编程设备包括控制器，保护系统，静态存储元件和锁存器，其可被称为基于锁存器的一次可编程（OTP）元件。 在一个示例中，静态存储元件包括用作电阻元件的薄栅极氧化物，其根据其是否被熔断将锁存器设置为两种状态之一。

公开(公告)号：US20050258482A1

公开(公告)日：2005-11-24

申请号：US11094269

申请日：2005-03-31

申请人： Akira Ito ,  Douglas Smith ,  Myron Buer

发明人： Akira Ito ,  Douglas Smith ,  Myron Buer

IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/112 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.

摘要翻译： 反熔丝器件包括衬底和形成在衬底中的侧向间隔开的源极和漏极区域。 在源区和漏区之间形成通道。 在通道上形成栅极和栅极氧化物，并且在沟道中形成轻掺杂的源极和漏极延伸区域。 轻掺杂的源极和漏极区域分别从源极和漏极区域延伸穿过沟道，占据通道的主要部分。 通过向栅极和源极区域和漏极区域中的至少一个施加电力来执行反熔丝的编程，以分解栅极氧化物，从而最小化栅极和沟道之间的电阻。

公开(公告)号：US06898103B2

公开(公告)日：2005-05-24

申请号：US10352417

申请日：2003-01-28

申请人： Douglas D. Smith ,  Myron Buer ,  Laurentiu Vasiliu ,  Bassem Radieddine

发明人： Douglas D. Smith ,  Myron Buer ,  Laurentiu Vasiliu ,  Bassem Radieddine

IPC分类号： G11C8/16 ,  G11C11/412 ,  G11C11/419 ,  G11C17/16 ,  G11C17/00

CPC分类号： G11C17/18 ,  G11C8/16 ,  G11C11/412 ,  G11C11/419 ,  G11C17/16

摘要： The present invention relates to a programmable memory cell and a method of setting a state for a programmable memory cell. The memory cell includes two thin gated fuses adapted to set the state of the memory cell. A level shifter device is connected to the gated fuses and is adapted to stand off a high voltage when setting the state of the memory cell. At least one switch transistor is connected to at least the level shifter device and is adapted to select at least one of the gated fuses, enabling a high voltage to be communicated thereto, thus setting the state of the memory cell.

摘要翻译： 本发明涉及一种可编程存储单元和一种设置可编程存储单元的状态的方法。 存储单元包括适于设置存储单元的状态的两个薄门控保险丝。 电平移位器装置连接到门控保险丝，并且在设置存储器单元的状态时适于高压放电。 至少一个开关晶体管连接到至少电平移位器装置，并且适于选择门控保险丝中的至少一个，使得能够将高电压传送到其中，从而设置存储器单元的状态。

公开(公告)号：US20050091477A1

公开(公告)日：2005-04-28

申请号：US10996140

申请日：2004-11-23

申请人： Mark Slamowitz ,  Douglas Smith ,  David Knebelsberger ,  Myron Buer

发明人： Mark Slamowitz ,  Douglas Smith ,  David Knebelsberger ,  Myron Buer

IPC分类号： G11C8/16 ,  G11C11/412 ,  G11C11/419 ,  G06F15/00

CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/063

摘要： The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

摘要翻译： 本发明涉及一种多端口寄存器文件存储器或SRAM，它包括多个存储元件和其他同步或异步操作的电路。 存储元素以行和列排列并存储数据。 两个读端口对耦合到每个存储元件和差分感测装置或电路。 读取端口以隔离的方式耦合到存储元件，使得多个单元格能够以这样的行和列排列。 感测装置适于感测小的电压摆幅。 列复用电路耦合到每个列和感测装置。 随着电源电压由于总线掉落或电感效应而降低，性能不会异常降低。

公开(公告)号：US06744660B2

公开(公告)日：2004-06-01

申请号：US10418254

申请日：2003-04-17

申请人： Douglas D. Smith ,  Myron Buer ,  Bassem Radieddine

发明人： Douglas D. Smith ,  Myron Buer ,  Bassem Radieddine

IPC分类号： G11C1100

CPC分类号： H01L23/5256 ,  G11C17/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a method of setting a state of a one-time programmable memory device having at least one memory cell with a thin gate-ox fuse element having an oxide of about 2.5 nm thick or less using a high voltage switch. The method comprises switching in a high programming voltage into the memory cell using such high voltage switch, setting the state of the thin gate-ox fuse element.

摘要翻译： 本发明涉及一种使用高电压开关来设置具有至少一个存储单元的状态的方法，所述存储单元具有厚度为2.5nm或更小的氧化物的薄栅氧化物熔丝元件。 该方法包括使用这种高电压开关将高编程电压切换到存储器单元中，从而设定薄栅极氧保险丝元件的状态。

公开(公告)号：US5748070A

公开(公告)日：1998-05-05

申请号：US689906

申请日：1996-08-15

申请人： Gordon W. Priebe ,  Myron Buer

发明人： Gordon W. Priebe ,  Myron Buer

IPC分类号： G11C11/419 ,  G06F7/02 ,  G06F11/16 ,  G11C15/00 ,  H03K5/24

CPC分类号： H03K5/2481 ,  G06F7/02 ,  G11C15/00 ,  G11C29/38

摘要： A multiple match detection circuit including an array of N and P-channel pull-up and pull-down devices receiving a corresponding array of hit line signals for developing complementary bit line signals, which are provided to the respective inputs of a differential comparator. Respective buffers drive the bit line signals to a maximum voltage differential in normal mode. For each hit line asserted, the pull-up and pull-down devices modify the voltage of the corresponding bit line voltage between the bit lines by an incremental amount, thereby decreasing the differential. Any single hit line does not cause enough of a voltage change to reverse the polarity of the differential voltage between the bit lines. However, if more than one hit line is asserted, the combined incremental change of voltage due to activation of two or more pull-up and pull-down devices is greater than the maximum voltage differential between the bit line signals asserted by the buffers, causing the bit line differential voltage to reverse polarity. The differential comparator detects the reversal of polarity of the bit line differential voltage and asserts an error signal. The multiple detection circuit further includes a transmission gate, which selectively equalizes charge on the bit lines, and isolation devices, which provide level shifting, prior to detection by the differential amplifier to thereby increase the speed of detection.

摘要翻译： 多重匹配检测电路包括N和P沟道上拉和下拉器件的阵列，其接收相应阵列的命中线信号，用于开发互补的位线信号，该互补位线信号被提供给差分比较器的相应输入端。 各个缓冲器在正常模式下将位线信号驱动到最大电压差。 对于每个命中线断言，上拉和下拉器件将位线之间的相应位线电压的电压修改一个增量，从而减小差分。 任何一条命中线都不会产生足够的电压变化来反转位线之间的差分电压的极性。 然而，如果多于一个命中线被断言，由于两个或多个上拉和下拉器件的激活而导致的组合的电压增量变化大于由缓冲器断言的位线信号之间的最大电压差，导致 位线差分电压反向极性。 差分比较器检测位线差分电压的极性反转，并产生一个误差信号。 多重检测电路还包括传输门，其选择性地均衡位线上的电荷，以及在由差分放大器检测之前提供电平移位的隔离装置，从而提高检测速度。