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公开(公告)号：US06421267B1
公开(公告)日：2002-07-16
申请号：US09840709
申请日：2001-04-24
申请人： Nai-Ping Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Ho-Chun Liou
发明人： Nai-Ping Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Ho-Chun Liou
IPC分类号： G11C1134
CPC分类号： G11C16/3495 , G11C16/0483 , G11C16/10 , G11C2216/16
摘要： A memory array architecture includes a plurality of memory cells formed into rows and columns. A plurality of bit lines is connected to the memory cells through select transistors. By disposing adjacent bit lines into different metal layers or alternatively interlocating adjacent bit lines, the coupling effect between bit lines can be effectively reduced, and thus can improve reading speed of memory while performing read operation.
摘要翻译： 存储器阵列结构包括形成行和列的多个存储单元。 多个位线通过选择晶体管连接到存储单元。 通过将相邻的位线布置在不同的金属层中或者可选地相互位置相邻的位线，可以有效地减少位线之间的耦合效应，从而可以在执行读取操作时提高存储器的读取速度。
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公开(公告)号：US06396753B1
公开(公告)日：2002-05-28
申请号：US09826497
申请日：2001-04-05
申请人： Chun-Hsiung Hung , Nai-Ping Kuo , Tu-Shun Chen , Ho-Chun Liou
发明人： Chun-Hsiung Hung , Nai-Ping Kuo , Tu-Shun Chen , Ho-Chun Liou
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C16/04 , G11C2207/104
摘要： A method and structure for testing embedded flash memory including a memory array and a logic element. A control transistor is disposed and is connected between a sense amplifier and an I/O buffer in the memory array, and a speed control pin connected to the logic element in one terminal is coupled to the gate terminal of the control transistor in the other terminal to switch the control transistor on or off. Turning off the control transistor after a test time by the speed control pin closes the channel between the sense amplifier and I/O buffer, and an output signal from the memory array to a test system connected to the logic element is detected with the test system to determine an access time of the memory array.
摘要翻译： 一种用于测试包括存储器阵列和逻辑元件的嵌入式闪速存储器的方法和结构。 控制晶体管被设置并连接在存储器阵列中的读出放大器和I / O缓冲器之间，并且连接到一个端子中的逻辑元件的速度控制引脚耦合到另一个端子中的控制晶体管的栅极端子 开关控制晶体管。 通过速度控制引脚在测试时间后关闭控制晶体管，关闭读出放大器和I / O缓冲器之间的通道，并从测试系统检测到从存储器阵列到连接到逻辑元件的测试系统的输出信号 以确定存储器阵列的访问时间。
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公开(公告)号：US09159434B2
公开(公告)日：2015-10-13
申请号：US13458485
申请日：2012-04-27
摘要： A bit line bias circuit of a memory architecture includes a varying voltage drop. In some embodiments, the voltage drop can depend on the threshold voltage of the memory cell selected to be read, or on the sense current flowing through the memory cell selected to be read.
摘要翻译： 存储器架构的位线偏置电路包括变化的电压降。 在一些实施例中，电压降可以取决于选择要读取的存储器单元的阈值电压，或取决于流经选择读取的存储器单元的检测电流。
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公开(公告)号：US08879332B2
公开(公告)日：2014-11-04
申请号：US13370833
申请日：2012-02-10
IPC分类号： G11C16/06
摘要： The configurations of a flash memory having a read tracking clock and method thereof are provided. The proposed flash memory includes a first and a second storage capacitors, a first current source providing a first current flowing through the first storage capacitor, a second current source providing a second current flowing through the second storage capacitor, and a comparator electrically connected to the first and the second current sources, and sending out a signal indicating a developing time being accomplished when the second current is larger than the first current.
摘要翻译： 提供具有读追踪时钟及其方法的闪速存储器的配置。 所提出的闪速存储器包括第一和第二存储电容器，提供流过第一存储电容器的第一电流的第一电流源，提供流过第二存储电容器的第二电流的第二电流源，以及电连接到 第一和第二电流源，并且当第二电流大于第一电流时发出指示正在完成的显影时间的信号。
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公开(公告)号：US08736358B2
公开(公告)日：2014-05-27
申请号：US12840943
申请日：2010-07-21
CPC分类号： G05F1/561
摘要： A current source providing an output current with a fixed current range includes a bias circuit, a resistor, a current mirror, and a controller. The bias circuit provides a first voltage weighted with a first tunable coefficient and a second voltage weighted with a second tunable coefficient. The resistor has a tunable resistance for determining a bias current according to a voltage difference between the first and the second voltages and the tunable resistance. The current mirror generates the output current according to the bias current. The controller adjusts the tunable resistance and one of the first and the second tunable coefficients to achieve a voltage-current coefficient with different values, while the bias current and the output current are kept within a fixed current range.
摘要翻译： 提供具有固定电流范围的输出电流的电流源包括偏置电路，电阻器，电流镜和控制器。 偏置电路提供用第一可调系数和第二可调系数加权的第二电压加权的第一电压。 电阻器具有根据第一和第二电压之间的电压差以及可调谐电阻来确定偏置电流的可调电阻。 电流镜根据偏置电流产生输出电流。 控制器调节可调谐电阻和第一和第二可调谐系数之一，以实现具有不同值的电压 - 电流系数，而偏置电流和输出电流保持在固定电流范围内。
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56.发明授权Memory program discharge circuit of bit lines with multiple discharge paths 有权具有多个放电路径的位线的存储器程序放电电路公开(公告)号：US08537630B2
公开(公告)日：2013-09-17
申请号：US13722530
申请日：2012-12-20
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/06 , G11C16/24 , G11C16/26 , Y10T29/49117
摘要： A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation.
摘要翻译： 存储器集成电路具有非易失性存储单元的阵列，访问非易失性存储单元阵列的位线和位线放电电路。 在编程操作期间，位线在同一时间对于位线具有多个放电路径。
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57.发明申请Memory Program Discharge Circuit of Bit Lines With Multiple Discharge Paths 有权具有多个放电路径的位线的存储器程序放电电路公开(公告)号：US20130107637A1
公开(公告)日：2013-05-02
申请号：US13722530
申请日：2012-12-20
CPC分类号： G11C7/12 , G11C7/06 , G11C16/24 , G11C16/26 , Y10T29/49117
摘要： A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation.
摘要翻译： 存储器集成电路具有非易失性存储单元的阵列，访问非易失性存储单元阵列的位线和位线放电电路。 在编程操作期间，位线在同一时间对于位线具有多个放电路径。
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公开(公告)号：US08429335B2
公开(公告)日：2013-04-23
申请号：US12577891
申请日：2009-10-13
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5642 , G11C2211/5647
摘要： Provided is a MLC (Multi-level cell) memory device, comprising: a memory array, including a plurality of groups each storing a plurality of bits; and an inverse bit storage section, storing a first inverse bit data including a plurality of inverse bits, the plurality of bits in the same group in the memory array being related to a respective inverse bit.
摘要翻译： 提供了一种MLC（多级单元）存储器件，包括：存储器阵列，包括多个组，每组存储多个位; 以及反比特存储部，存储包括多个反比特的第一反比特数据，存储器阵列中的同一组中的多个比特与相应的反比特相关。
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公开(公告)号：US20120319756A1
公开(公告)日：2012-12-20
申请号：US13596953
申请日：2012-08-28
IPC分类号： H03L5/00
CPC分类号： H03K19/018528 , G05F3/02 , G06F1/04 , G06F1/08 , G06F1/10 , G06F1/12 , H03K19/0175 , H03L5/00
摘要： The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.
摘要翻译： 集成电路的时钟电路具有诸如温度，接地噪声和功率噪声的变化。 改进的时钟集成电路的各个方面解决了温度，地面噪声和功率噪声中的一个或多个变化。
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公开(公告)号：US20110157986A1
公开(公告)日：2011-06-30
申请号：US13041642
申请日：2011-03-07
IPC分类号： G11C16/06
CPC分类号： G11C29/02 , G11C8/08 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： A memory and an operating method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely.
摘要翻译： 在其中提供存储器及其操作方法。 当搜索存储器的阈值电压分布的边界时，将校正由存储器的尾部位产生的数据错误。 因此，感测窗口可以更宽，并且可以精确地确定阈值电压分布的边界。
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