公开(公告)号：US20130147472A1

公开(公告)日：2013-06-13

申请号：US13314097

申请日：2011-12-07

Applicant: William French ,  Philipp Lindorfer ,  Peter J. Hopper ,  Roozbeh Parsa ,  Andrew James West ,  Byron Jon Roderick Shulver

Inventor： William French ,  Philipp Lindorfer ,  Peter J. Hopper ,  Roozbeh Parsa ,  Andrew James West ,  Byron Jon Roderick Shulver

IPC: G01R33/02 ,  H01L21/58 ,  H01L29/82

CPC classification number: G01R33/032 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/014 ,  H01L2924/00

Abstract: The cost and size of an atomic magnetometer are reduced by attaching a vapor cell structure that has a vapor cell cavity to a base die that has a laser light source that outputs light to the vapor cell cavity, and attaching a photo detection die that has a photodiode to the vapor cell structure to detect light from the laser light source that passes through the vapor cell cavity.

Abstract translation: 原子磁力计的成本和尺寸通过将具有蒸汽单元空腔的蒸汽单元结构附接到具有将光输出到蒸气腔空腔的激光源的基座上而被降低，以及附接具有 光电二极管到蒸汽池结构以检测来自通过蒸气室腔的激光源的光。

公开(公告)号：US08344394B1

公开(公告)日：2013-01-01

申请号：US12584904

申请日：2009-09-15

Applicant: Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

Inventor： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

IPC: H01L33/00

CPC classification number: H01L33/0012 ,  H01L33/34 ,  H01L33/647

Abstract: A circuit includes multiple doped regions in a substrate. A first of the doped regions has a tip proximate to a second of the doped regions and is separated from the second doped region by an intrinsic region to form a P-I-N structure. The circuit also includes first and second electrodes electrically coupled to the first and second doped regions, respectively. The electrodes are configured to supply voltages to the first and second doped regions to reverse bias the P-I-N structure and generate light. The first doped region could include multiple tips, the second doped region could include multiple tips, and each tip of the first doped region could be proximate to one of the tips of the second doped region to form multiple P-I-N structures. The P-I-N structure could also be configured to operate in double avalanche injection conductivity mode with internal positive feedback.

Abstract translation: 电路包括衬底中的多个掺杂区域。 掺杂区域中的第一个具有靠近第二掺杂区域的尖端，并且与第二掺杂区域分离出本征区域以形成P-I-N结构。 电路还包括分别电耦合到第一和第二掺杂区域的第一和第二电极。 电极被配置为向第一和第二掺杂区域提供电压以反向偏置P-I-N结构并产生光。 第一掺杂区域可以包括多个尖端，第二掺杂区域可以包括多个尖端，并且第一掺杂区域的每个尖端可以接近第二掺杂区域的尖端之一以形成多个P-I-N结构。 P-I-N结构也可以被配置为在具有内部正反馈的双雪崩注入电导模式下工作。

公开(公告)号：US07754505B1

公开(公告)日：2010-07-13

申请号：US12284290

申请日：2008-09-19

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  William French ,  Vladislav Vashchenko

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  William French ,  Vladislav Vashchenko

IPC: H01L21/00

CPC classification number: H01L33/387 ,  H01L33/04 ,  H01L33/08

Abstract: A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.

Abstract translation: 形成硅基发光结构作为发光p-n结的高密度阵列，其显着增加在平坦区域中发射的光的强度。 使用标准CMOS处理方法形成p-n结，并响应于产生雪崩击穿和雪崩电流的施加电压而发光。

公开(公告)号：US07462874B1

公开(公告)日：2008-12-09

申请号：US11403516

申请日：2006-04-13

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  William French ,  Vladislav Vashchenko

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  William French ,  Vladislav Vashchenko

IPC: H01L33/00

CPC classification number: H01L33/387 ,  H01L33/04 ,  H01L33/08

Abstract: A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.

Abstract translation: 形成硅基发光结构作为发光p-n结的高密度阵列，其显着增加在平坦区域中发射的光的强度。 使用标准CMOS处理方法形成p-n结，并响应于产生雪崩击穿和雪崩电流的施加电压而发光。

公开(公告)号：US07375579B1

公开(公告)日：2008-05-20

申请号：US11198796

申请日：2005-08-04

Applicant: Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

Inventor： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

IPC: H01H37/76

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: In a fuse-based programmable circuit block, the poly-fuse is burned out by making use of a snapback device connected in series with the poly-fuse.

Abstract translation: 在基于熔丝的可编程电路块中，通过使用与多熔丝串联连接的快速恢复装置将多晶硅熔断器烧掉。

公开(公告)号：US07301436B1

公开(公告)日：2007-11-27

申请号：US11274491

申请日：2005-11-14

Applicant: Peter J. Hopper ,  Peter Johnson ,  Philipp Lindorfer

Inventor： Peter J. Hopper ,  Peter Johnson ,  Philipp Lindorfer

IPC: H01C13/00

CPC classification number: H01L23/5228 ,  H01L24/02 ,  H01L27/0802 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19043

Abstract: An apparatus and method for using anti-fuse bond pads used to provide trimmed resistor values to the input terminals of circuits on an integrated circuit die. The apparatus and method comprises fabricating on a semiconductor integrated circuit a resistive network. The resistive network includes a first terminal, a second terminal and a resistor coupled between the two terminals. An anti-fuse bond pad and a trimming resistor are coupled between the first terminal and the second terminal. The trimming resistor is configured to be electrically coupled between the first terminal and the second terminal when a ball bond is formed on the anti-fuse bond pad. In various embodiments, a plurality of the anti-fuse bond pads and trimming resistors may be coupled between the two terminals. By selectively forming ball bonds on the plurality of anti-fuse bond pads, the resistance of the network can be selectively trimmed as needed.

Abstract translation: 一种用于使用反熔丝接合焊盘的装置和方法，用于向集成电路管芯上的电路的输入端提供修整的电阻值。 该装置和方法包括在半导体集成电路上制造电阻网络。 电阻网络包括耦合在两个端子之间的第一端子，第二端子和电阻器。 反熔丝接合焊盘和微调电阻耦合在第一端子和第二端子之间。 当在反熔丝接合焊盘上形成球焊时，微调电阻被配置为电耦合在第一端子和第二端子之间。 在各种实施例中，多个反熔丝接合焊盘和微调电阻器可以耦合在两个端子之间。 通过在多个反熔丝接合焊盘上选择性地形成球键，可以根据需要选择性地修整网络的电阻。

公开(公告)号：US07298653B1

公开(公告)日：2007-11-20

申请号：US10873872

申请日：2004-06-21

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

IPC: G11C11/34

CPC classification number: G11C29/02 ,  G11C16/04 ,  G11C16/12 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004

Abstract: In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their erased states and in their programmed states, it is possible to define more than one read voltage and thus provide cells that an store multiple values and even analog values.

Abstract translation: 在EEPROM阵列中，单元被预充电或预擦除，使得它们将均匀地响应于相同的读取电压电平。 通过明确定义其擦除状态和编程状态下的单元的阈值电压，可以定义多个读取电压，从而提供存储多个值和甚至模拟值的单元。

公开(公告)号：US07250841B1

公开(公告)日：2007-07-31

申请号：US11213155

申请日：2005-08-25

Applicant: Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Philipp Lindorfer

Inventor： Peter J. Hopper ,  Peter Johnson ,  Kyuwoon Hwang ,  Philipp Lindorfer

IPC: H01F27/02

CPC classification number: H01F17/0033 ,  H01F41/046 ,  H01L23/5227 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A micro-electromechanical system (MEMS) inductor is formed in a saucer shape that completely surrounds a magnetic core structure which is formed from a ferromagnetic material. In addition, an array of MEMS inductors can be formed by dividing up the saucer-shaped MEMS inductor into a number of electrically-isolated MEMS inductor wedges.

Abstract translation: 微机电系统（MEMS）电感器形成为完全围绕由铁磁材料形成的磁芯结构的碟形形状。 此外，可以通过将碟形MEMS电感器分成多个电隔离的MEMS电感器楔形物来形成MEMS电感器阵列。

公开(公告)号：US07221608B1

公开(公告)日：2007-05-22

申请号：US10957986

申请日：2004-10-04

Applicant: Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

Inventor： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/403 ,  G11C2211/4065

Abstract: The snapback characteristics of the parasitic NPN structure inside an NMOS device are used to write and store information in the device by periodically triggering the device from the high impedance state to the low impedance state using the self turn-on characteristics of the device under elevated voltage. To minimize power consumption, and thus overheating, in the “on” state, a pulsed mode operation is combined with dV/dt triggering powering the device at a constant Vdd pulse amplitude.

Abstract translation: NMOS器件内的寄生NPN结构的快速恢复特性用于通过在高电压下使器件的自启动特性周期性地将器件从高阻抗状态触发到低阻抗状态来将信息写入和存储在器件中 。 为了最小化功率消耗并因此过热，在“导通”状态下，将脉冲模式操作与dV / dt触发相结合，以恒定的Vdd脉冲幅度向器件供电。

公开(公告)号：US07180133B1

公开(公告)日：2007-02-20

申请号：US11016147

申请日：2004-12-17

Applicant: Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski ,  Philipp Lindorfer

Inventor： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski ,  Philipp Lindorfer

IPC: H01L29/76

CPC classification number: H01L29/0847 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/7835

Abstract: In a method and structure for a high voltage LDMOS with reduced hot carrier degradation, the thick field oxide is eliminated and a reduced surface field achieved instead by including adjacent p+ and n+ regions in the drain well and shorting these regions to each other, or by including a p+ region in the drain well and biasing it to a positive voltage relative to the source voltage.

Abstract translation: 在具有减少的热载流子劣化的高电压LDMOS的方法和结构中，消除了厚场氧化物，并且通过在漏极阱中包括相邻的p +和n +区域而将这些区域彼此短路，或者通过 包括漏极阱中的p +区，并将其偏压到相对于源极电压的正电压。