公开(公告)号：US07209503B1

公开(公告)日：2007-04-24

申请号：US10838671

申请日：2004-05-03

申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

IPC分类号： H01S5/00

CPC分类号： H01L27/1446 ,  H01L27/146

摘要： An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive regions via the photovoltaic effect.

摘要翻译： 集成电路通过将形成为接收电源电压的PMOS晶体管的p +源极区域等导电区域暴露于来自光源的光能来供电。 导电区域用作通过光电效应在导电区域上产生电压的光电二极管。

公开(公告)号：US07113427B1

公开(公告)日：2006-09-26

申请号：US11076711

申请日：2005-03-09

申请人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer

发明人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/12 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/7881

摘要： NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.

摘要翻译： 用于存储三个电荷电平的NVM单元：一个擦除和两个编程状态。 该单元包括提供具有平坦区域或第二峰值的形状的栅极电流对栅极电压曲线的晶体管结构。 为了提供这样的结构，一个实施例组合了具有不同阈值电压的两个并联晶体管，另一实施例使用一个具有可变掺杂的晶体管 栅极电流曲线提供两个编程区域。 对第一状态进行编程包括在一个通道上施加电压，使第一个编程区中的栅极电压升高，然后将其向下斜坡。 对第二状态进行编程包括在通道上施加电压，将栅极电压升高到第一编程区并进入第二编程区，然后将其向下斜坡。 可以选择先将电压降低，然后关闭通道上的电压。

公开(公告)号：US07180379B1

公开(公告)日：2007-02-20

申请号：US10838485

申请日：2004-05-03

申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

IPC分类号： G01N21/00

CPC分类号： G06F1/105

摘要： A synchronous clock signal is generated in a large number of local clock circuits at the same time by exposing photoconductive regions in each local clock circuit to a pulsed light source that operates at a fixed frequency. The photoconductive regions generate photoconductive currents which are sufficient to cause a logic inverter to switch states.

摘要翻译： 通过将每个本地时钟电路中的光电导区域暴露于以固定频率工作的脉冲光源，同时在多个本地时钟电路中产生同步时钟信号。 光电导区产生足以导致逻辑逆变器切换状态的光电流。

公开(公告)号：US07050314B1

公开(公告)日：2006-05-23

申请号：US10625961

申请日：2003-07-23

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski ,  Philipp Lindorfer

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski ,  Philipp Lindorfer

IPC分类号： H02M3/18

CPC分类号： H02M3/07

摘要： A charge pump circuit in which at least one of the switching elements takes the form of a LVTSCR. The switching on and off of the LVTSCRs may be achieved by making use of a pulsed input and relying on the triggering and holding voltages of the LVTSCRs to switch on and off.

摘要翻译： 一种电荷泵电路，其中至少一个开关元件采取LVTSCR的形式。 LVTSCR的接通和断开可以通过使用脉冲输入并依靠LVTSCR的触发和保持电压来接通和关断来实现。

公开(公告)号：US07298653B1

公开(公告)日：2007-11-20

申请号：US10873872

申请日：2004-06-21

申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

IPC分类号： G11C11/34

CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C16/12 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004

摘要： In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their erased states and in their programmed states, it is possible to define more than one read voltage and thus provide cells that an store multiple values and even analog values.

摘要翻译： 在EEPROM阵列中，单元被预充电或预擦除，使得它们将均匀地响应于相同的读取电压电平。 通过明确定义其擦除状态和编程状态下的单元的阈值电压，可以定义多个读取电压，从而提供存储多个值和甚至模拟值的单元。

公开(公告)号：US07180133B1

公开(公告)日：2007-02-20

申请号：US11016147

申请日：2004-12-17

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski ,  Philipp Lindorfer

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski ,  Philipp Lindorfer

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/7835

摘要： In a method and structure for a high voltage LDMOS with reduced hot carrier degradation, the thick field oxide is eliminated and a reduced surface field achieved instead by including adjacent p+ and n+ regions in the drain well and shorting these regions to each other, or by including a p+ region in the drain well and biasing it to a positive voltage relative to the source voltage.

摘要翻译： 在具有减少的热载流子劣化的高电压LDMOS的方法和结构中，消除了厚场氧化物，并且通过在漏极阱中包括相邻的p +和n +区域而将这些区域彼此短路，或者通过 包括漏极阱中的p +区，并将其偏压到相对于源极电压的正电压。

公开(公告)号：US20070066002A1

公开(公告)日：2007-03-22

申请号：US11601485

申请日：2006-11-17

申请人： Peter Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

发明人： Peter Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/78

摘要： An implant is added at the interface between the source region of an MOS transistor and the well material to improve dynamic IR drop performance. The additional implant raises the underlying capacitance of the source region. This, in turn, provides for an increase in charge storage which, in turn, provides for an improved level of protection against dynamic IR drop.

摘要翻译： 在MOS晶体管的源极区域和阱材料之间的界面处添加植入物，以改善动态IR滴落性能。 额外的植入物提高了源区域的底层电容。 这又反过来提供了电荷存储的增加，这进而提供了防止动态IR降低的改进的防护等级。

公开(公告)号：US07479435B1

公开(公告)日：2009-01-20

申请号：US11007565

申请日：2004-12-08

申请人： Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer ,  Andy Strachan

发明人： Peter J. Hopper ,  Vladislav Vashchenko ,  Philipp Lindorfer ,  Andy Strachan

IPC分类号： H01L29/788

CPC分类号： H01L21/26586 ,  H01L21/2652 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0847

摘要： A MOS transistor and subsurface collectors can be formed by using a hard mask and precisely varying the implant angle, rotation, dose, and energy. In this case, a particular atomic species can be placed volumetrically in a required location under the hard mask. The dopant can be implanted to form sub-silicon volumes of arbitrary shapes, such as pipes, volumes, hemispheres, and interconnects.

摘要翻译： 可以通过使用硬掩模并精确地改变植入角度，旋转，剂量和能量来形成MOS晶体管和地下收集器。 在这种情况下，特定的原子物质可以体积地放置在硬掩模下的所需位置。 可以将掺杂剂注入以形成任意形状的子硅体积，例如管道，体积，半球和互连。

公开(公告)号：US07394133B1

公开(公告)日：2008-07-01

申请号：US11216774

申请日：2005-08-31

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer

IPC分类号： H01L29/72

CPC分类号： H01L27/0262 ,  H01L29/0692 ,  H01L29/7436 ,  H01L29/87

摘要： In an ESD protection structure, dual direction ESD protection is provided by forming an n-well isolation ring around an NMOS device so that the p-well in which the NMOS drain is formed is isolated from the underlying p-substrate by the n-well isolation ring. By forming the n-well isolation ring the p-n-p-n structure of an embedded SCR for reverse ESD protection is provided. The width of the n-well isolation ring and its spacing from the NMOS drain are adjusted to provide the desired SCR parameters.

摘要翻译： 在ESD保护结构中，通过在NMOS器件周围形成n阱隔离环来提供双向ESD保护，使得形成NMOS漏极的p阱通过n阱与下面的p衬底隔离 隔离环。 通过形成n阱隔离环，提供了用于反向ESD保护的嵌入式SCR的p-n-p-n结构。 调整n阱隔离环的宽度及其与NMOS漏极的间隔，以提供所需的SCR参数。

公开(公告)号：US07218555B2

公开(公告)日：2007-05-15

申请号：US11242094

申请日：2005-10-03

申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

IPC分类号： G11C11/34 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/14603 ,  H01L27/14609

摘要： The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.

摘要翻译： 成像单元的积分周期或成像单元暴露于光能的时间通过利用单聚电子可编程只读存储器（EPROM）结构捕获光能而大大增加。 光能从EPROM结构的沟道区形成光电子。 光生成的电子然后被加速成具有电离碰撞，其进而导致电子以与通道区域捕获的光子数成正比的速率注入到EPROM结构的浮动栅极上。