公开(公告)号：US07724575B2

公开(公告)日：2010-05-25

申请号：US12035028

申请日：2008-02-21

申请人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

发明人： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： In one aspect a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

摘要翻译： 在一个方面，提供可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。

公开(公告)号：US20090147575A1

公开(公告)日：2009-06-11

申请号：US12366266

申请日：2009-02-05

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C16/00 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

摘要翻译： 在具有串行感测操作的NOR闪存器件以及NOR闪存器件中的数据位检测方法中，器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

公开(公告)号：US20090129165A1

公开(公告)日：2009-05-21

申请号：US12191434

申请日：2008-08-14

申请人： Chang Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

发明人： Chang Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/16

摘要： Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which may be interleaved with the first plurality of nonvolatile memory cells. This operation to selectively erase the first plurality of nonvolatile memory cells may include erasing the first plurality of nonvolatile memory cells while simultaneously biasing the second plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the second plurality of nonvolatile memory cells. The operation to selectively erase the second plurality of nonvolatile memory cells may include erasing the second plurality of nonvolatile memory cells while simultaneously biasing the first plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the first plurality of nonvolatile memory cells.

摘要翻译： 操作电荷阱非易失性存储装置的方法包括通过选择性地擦除第一串中的第一多个非易失性存储单元，然后选择性地擦除第一串中的第二多个非易失性存储单元来擦除第一串非易失性存储单元的操作， 其可以与第一多个非易失性存储器单元交错。 选择性地擦除第一多个非易失性存储单元的操作可以包括擦除第一多个非易失性存储单元，同时在禁止擦除第二多个非易失性存储单元的阻塞条件下同时偏置第二多个非易失性存储单元。 选择性地擦除第二多个非易失性存储单元的操作可以包括擦除第二多个非易失性存储单元，同时在禁止擦除第一多个非易失性存储单元的阻塞条件下同时偏置第一多个非易失性存储单元。

公开(公告)号：US20080291738A1

公开(公告)日：2008-11-27

申请号：US12186087

申请日：2008-08-05

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G11C16/06 ,  G05F1/10 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C5/145 ,  G11C16/0483

摘要： Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed.

摘要翻译： 产生用于编程非易失性存储器件的编程电压的方法包括产生初始电压并响应于初始电压产生第一斜变电压。 第一斜坡电压的斜坡速度比初始电压的斜坡速度慢。 响应于第一斜坡电压产生第二斜坡电压。 第二斜坡电压具有比第一斜坡电压更低的纹波。 输出第二斜坡电压作为编程非易失性存储器件的编程电压。 一个编程电压发生电路包括：一个编程电压产生单元，被配置为产生一个初始电压;一个斜坡电路，被配置为产生一个响应初始电压的第一斜坡电压;以及一个电压控制单元，被配置为产生一个具有相对低纹波的第二斜坡电压 并且响应于第一斜坡电压的电压电平而输出第一斜坡电压或第二斜坡电压。 还公开了包括程序电压产生电路的半导体存储器件。

公开(公告)号：US20080253182A1

公开(公告)日：2008-10-16

申请号：US12145531

申请日：2008-06-25

申请人： Moo-Sung Kim ,  Young-Ho Lim

发明人： Moo-Sung Kim ,  Young-Ho Lim

IPC分类号： G11C16/06

CPC分类号： G11C16/12 ,  G11C8/08 ,  G11C16/0483

摘要： A NAND flash memory device and a programming method thereof capable of improving a program speed during a multi-level cell programming operation are provided. The device performs a programming operation using an ISPP method. Additionally, the device includes a memory cell storing multi-bit data; a program voltage generating circuit generating a program voltage to be supplied to the memory cell; and a program voltage controller controlling a start level of the program voltage. The device supplies an LSB start voltage to a selected word line during an LSB program, and an MSB start voltage higher than the LSB start voltage to the selected word line during an MSB program.

摘要翻译： 提供一种能够在多级单元编程操作期间提高编程速度的NAND快闪存储器件及其编程方法。 该设备使用ISPP方法执行编程操作。 另外，该设备包括存储多位数据的存储单元; 编程电压产生电路，产生要提供给存储单元的编程电压; 以及控制编程电压的起始电平的编程电压控制器。 在MSB程序期间，器件在LSB程序期间将LSB起始电压提供给所选择的字线，并在MSB程序期间向所选字线提供高于LSB起始电压的MSB启动电压。

公开(公告)号：US07403422B2

公开(公告)日：2008-07-22

申请号：US11500410

申请日：2006-08-08

申请人： Moo-Sung Kim ,  Young-Ho Lim

发明人： Moo-Sung Kim ,  Young-Ho Lim

IPC分类号： G11C16/06

CPC分类号： G11C16/12 ,  G11C8/08 ,  G11C16/0483

摘要： A NAND flash memory device and a programming method thereof capable of improving a program speed during a multi-level cell programming operation are provided. The device performs a programming operation using an ISPP method. Additionally, the device includes a memory cell storing multi-bit data; a program voltage generating circuit generating a program voltage to be supplied to the memory cell; and a program voltage controller controlling a start level of the program voltage. The device supplies an LSB start voltage to a selected word line during an LSB program, and an MSB start voltage higher than the LSB start voltage to the selected word line during an MSB program.

摘要翻译： 提供一种能够在多级单元编程操作期间提高编程速度的NAND快闪存储器件及其编程方法。 该设备使用ISPP方法执行编程操作。 另外，该设备包括存储多位数据的存储单元; 编程电压产生电路，产生要提供给存储单元的编程电压; 以及控制编程电压的起始电平的编程电压控制器。 在MSB程序期间，器件在LSB程序期间将LSB起始电压提供给所选择的字线，并在MSB程序期间向所选字线提供高于LSB起始电压的MSB启动电压。

公开(公告)号：US07362612B2

公开(公告)日：2008-04-22

申请号：US11598090

申请日：2006-11-13

申请人： Sang-gu Kang ,  Young-Ho Lim

发明人： Sang-gu Kang ,  Young-Ho Lim

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3459

摘要： The invention provides a programming method for a flash memory device including first and second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The program method may include programming memory cells, connected with a selected row and the second bitlines, with multi-bit data; determining whether the selected row is the last row; and reprogramming programmed memory cells connected with the selected row being the last row and the first bitlines when the determination result is that the selected row is the last row.

摘要翻译： 本发明提供了一种用于闪存器件的编程方法，其包括与多个存储器单元连接的第一和第二位线，用于存储指示多个状态之一的多位数据。 程序方法可以包括利用多位数据来编程与所选择的行和第二位线连接的存储器单元; 确定所选行是否是最后一行; 并且当确定结果是所选择的行是最后一行时，与所选行连接的编程存储器单元重新编程为最后一行和第一位。

公开(公告)号：US07298654B2

公开(公告)日：2007-11-20

申请号：US11133234

申请日：2005-05-20

申请人： Jae-Yong Jeong ,  Young-Ho Lim

发明人： Jae-Yong Jeong ,  Young-Ho Lim

IPC分类号： G11C11/34

CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445

摘要： Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.

摘要翻译： 公开了一种非易失性存储器件和擦除非易失性存储器件的方法。 同时将擦除电压施加到包含在非易失性存储器件中的多个扇区。 然后，针对多个扇区中的每一个依次执行擦除验证，并将擦除确认的结果存储在多个通过信息寄存器中。 根据存储在通过信息寄存器中的结果，同时重新擦除未成功擦除的扇区，然后顺序重新验证，直到在非易失性存储器件中不存在这样的“故障扇区”为止。 在从非易失性存储器件消除“故障扇区”时，对多个扇区中的每一个依次执行后编程操作。

公开(公告)号：US20070183210A1

公开(公告)日：2007-08-09

申请号：US11700834

申请日：2007-02-01

申请人： Ki-Hwan Choi ,  Young-Ho Lim

发明人： Ki-Hwan Choi ,  Young-Ho Lim

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： The present invention provides a program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The memory cells are subjected to a primary program operation. Those memory cells arranged within a specific region of respective states are subjected to a secondary program operation to have a threshold voltage equivalent to or higher than a verify voltage used in the primary program operation. Thus, although a threshold voltage distribution is widened due to an electric field coupling/F-poly coupling and HTS, a read margin between adjacent states may be sufficiently secured using the program method.

摘要翻译： 本发明提供了一种闪速存储装置的编程方法，其包括用于存储指示多个状态之一的多位数据的多个存储单元。 对存储器单元进行主程序操作。 布置在各个状态的特定区域内的那些存储单元经受二次编程操作，以具有等于或高于在主程序操作中使用的验证电压的阈值电压。 因此，尽管由于电场耦合/ F-poly耦合和HTS而使阈值电压分布变宽，但是可以使用编程方法充分确保相邻状态之间的读取余量。

公开(公告)号：US07227790B2

公开(公告)日：2007-06-05

申请号：US11263716

申请日：2005-11-01

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C7/06

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

摘要翻译： 在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。