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139 条记录 (耗时 0.028 秒)

    Local and remote network based management of an operating system-independent processor
    51.
    发明授权
    Local and remote network based management of an operating system-independent processor 有权
    本地和远程网络管理的独立于操作系统的处理器

    公开(公告)号：US07536479B2

    公开(公告)日：2009-05-19

    申请号：US10985123

    申请日：2004-11-09

    申请人： Ravi Sahita ,  Priya Rajagopal ,  David Durham ,  Scott Hahn ,  Carey Smith ,  Arvind Kumar

    发明人： Ravi Sahita ,  Priya Rajagopal ,  David Durham ,  Scott Hahn ,  Carey Smith ,  Arvind Kumar

    IPC分类号： G06F15/16

    CPC分类号： H04L29/12009 ,  H04L29/12405 ,  H04L61/2528

    摘要： In one embodiment, a method is provided. The method of this embodiment provides receiving one or more packets that are addressed to an alternate IP (Internet Protocol) address and that include a LADLC (local application data link control) address in a system having an operating system-independent processor (“service processor”) associated with the alternate IP address and an alternate DLC address, and an embedded network stack (“ENS”) of the service processor associated with a primary IP address; performing filtering to determine if the LADLC address matches the alternate DLC address; and if the LADLC address matches the alternate DLC address, then replacing the alternate IP address of the one or more packets with the primary IP address, and forwarding the one or more packets to the ENS.

    摘要翻译： 在一个实施例中，提供了一种方法。 该实施例的方法提供接收一个或多个寻址到备用IP（因特网协议）地址的分组，并且在具有与操作系统无关的处理器（“服务处理器”）的系统中包括LADLC（本地应用数据链路控制）地址 “）与备用IP地址和备用DLC地址相关联，以及与主IP地址相关联的服务处理器的嵌入式网络堆栈（”ENS“）; 执行滤波以确定LADLC地址是否与备用DLC地址匹配; 并且如果LADLC地址与备用DLC地址匹配，则用主IP地址替换一个或多个数据包的备用IP地址，并将一个或多个数据包转发到ENS。

    Method and an apparatus for managing power consumption of a server
    52.
    发明授权
    Method and an apparatus for managing power consumption of a server 有权
    用于管理服务器的功耗的方法和装置

    公开(公告)号：US07418608B2

    公开(公告)日：2008-08-26

    申请号：US10871587

    申请日：2004-06-17

    申请人： Arvind Kumar ,  David J. O'Shea

    发明人： Arvind Kumar ,  David J. O'Shea

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/171

    摘要： A method and an apparatus for managing power consumption of a server have been disclosed. In one embodiment, the method includes allowing a user to set a power management policy on a server, monitoring power consumption of a plurality of blades in the server, and automatically managing power consumption of the server in response to the power consumption of the plurality of blades based on the power management policy set by the user. Other embodiments have been claimed and described.

    摘要翻译： 已经公开了一种用于管理服务器的功耗的方法和装置。 在一个实施例中，该方法包括允许用户在服务器上设置电源管理策略，监视服务器中的多个刀片的功耗，以及响应于多个服务器的功耗而自动管理服务器的功耗 基于用户设置的电源管理策略。 已经要求和描述了其它实施例。

    Compact SRAMs and other multiple transistor structures
    54.
    发明授权
    Compact SRAMs and other multiple transistor structures 有权
    紧凑型SRAM和其他多晶体管结构

    公开(公告)号：US07365398B2

    公开(公告)日：2008-04-29

    申请号：US11055014

    申请日：2005-02-11

    申请人： Sandip Tiwari ,  Arvind Kumar

    发明人： Sandip Tiwari ,  Arvind Kumar

    IPC分类号： H01L29/76 ,  G11C11/00

    CPC分类号： H01L27/1104 ,  H01L27/11

    摘要： A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.

    摘要翻译： 高密度形式的静态随机存取存储器（SRAM）利用了硅两面的晶体管栅极和通过绝缘体上硅和三维集成的复杂形式实现的高互连性。 这种技术允许通过利用两侧的门的放置，在3D中形成常见的接触和密集的互连，从而非常紧凑地形成p沟道和n沟道器件。

    Internet based network topology discovery
    55.
    发明申请
    Internet based network topology discovery 审中-公开
    基于互联网的网络拓扑发现

    公开(公告)号：US20070294409A1

    公开(公告)日：2007-12-20

    申请号：US11893868

    申请日：2007-08-17

    申请人： Arvind Kumar

    发明人： Arvind Kumar

    IPC分类号： G06F15/173 ,  G06F17/30

    CPC分类号： H04L41/12 ,  H04L41/0266

    摘要： A system and method are provided for internet-based network topology discovery. A server in communication with a client, the server having a console having a managing device is provided to manage one or more network devices. A search engine is provided that is in communication with the managing device via a network including the Internet, the search engine capable of being accessed via the client. The console is used to formulate an Extensible Markup Language (XML) discovery information query, wherein the XML discovery information query is initiated automatically by the client. The console is further to send the XML discovery information query to the search engine to facilitate searching of discovery information relevant to the one or more network devices, wherein at least one of the one or more network devices includes an XML discovery information file, wherein at least one of the one or more network devices does not include the XML discovery information file. In response to sending the XML discovery information query, the console to receive one or more of the following via the search engine: first discovery information from the one or more network devices having the XML discovery information file, and second discovery information from a proxy device for the one or more network devices not including the XML discovery information files. The console is further used to generate a network topology map for the one or more network devices via the retrieved first and second discovery information.

    摘要翻译： 提供了一种基于互联网的网络拓扑发现的系统和方法。 提供与客户端通信的服务器，具有控制台的服务器具有管理设备以管理一个或多个网络设备。 提供了一种搜索引擎，其经由包括因特网的网络与管理设备通信，该搜索引擎能够经由客户机访问。 控制台用于制定可扩展标记语言（XML）发现信息查询，其中XML发现信息查询由客户端自动启动。 所述控制台还将所述XML发现信息查询发送到所述搜索引擎，以便于搜索与所述一个或多个网络设备相关的发现信息，其中所述一个或多个网络设备中的至少一个包括XML发现信息文件，其中， 一个或多个网络设备中的至少一个不包括XML发现信息文件。 响应于发送XML发现信息查询，控制台通过搜索引擎接收以下一个或多个：具有XML发现信息文件的一个或多个网络设备的第一发现信息和来自代理设备的第二发现信息 对于不包括XML发现信息文件的一个或多个网络设备。 控制台还用于通过检索的第一和第二发现信息为一个或多个网络设备生成网络拓扑图。

    Substrate solution for back gate controlled SRAM with coexisting logic devices
    56.
    发明申请
    Substrate solution for back gate controlled SRAM with coexisting logic devices 有权
    用于具有共存逻辑器件的背栅控制SRAM的衬底解决方案

    公开(公告)号：US20070138533A1

    公开(公告)日：2007-06-21

    申请号：US11311462

    申请日：2005-12-19

    申请人： Robert Dennard ,  Wilfried Haensch ,  Arvind Kumar ,  Robert Miller

    发明人： Robert Dennard ,  Wilfried Haensch ,  Arvind Kumar ,  Robert Miller

    IPC分类号： H01L29/76

    CPC分类号： H01L27/1108

    摘要： A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device

    摘要翻译： 一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂 提供了特定的水平，以提高不同器件区域内的FET器件的性能。 特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。 为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。 在源极/漏极区域之下具有低净掺杂的无均匀横向掺杂分布以及在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制

    Compact SRAMs and other multiple transistor structures
    58.
    发明申请
    Compact SRAMs and other multiple transistor structures 有权
    紧凑型SRAM和其他多晶体管结构

    公开(公告)号：US20050224994A1

    公开(公告)日：2005-10-13

    申请号：US11055014

    申请日：2005-02-11

    申请人： Sandip Tiwari ,  Arvind Kumar

    发明人： Sandip Tiwari ,  Arvind Kumar

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L31/062

    CPC分类号： H01L27/1104 ,  H01L27/11

    摘要： A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.

    摘要翻译： 高密度形式的静态随机存取存储器（SRAM）利用了硅两面的晶体管栅极和通过绝缘体上硅和三维集成的复杂形式实现的高互连性。 这种技术允许通过利用两侧的门的放置，在3D中形成常见的接触和密集的互连，从而非常紧凑地形成p沟道和n沟道器件。