公开(公告)号：US20080082736A1

公开(公告)日：2008-04-03

申请号：US11864684

申请日：2007-09-28

申请人： David Chow ,  Charles Lee ,  Abraham Ma ,  Frank Yu ,  Edward Lee ,  Ming-Shiang Shen

发明人： David Chow ,  Charles Lee ,  Abraham Ma ,  Frank Yu ,  Edward Lee ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7203 ,  G06F2212/7211

摘要： An electronic data flash card accessible by a host computer, includes a flash memory controller connected to a flash memory device, and an input-output interface circuit activated to establish a communication with the host. In an embodiment, the flash card uses a USB interface circuit for communication with the host. A flash memory controller includes an arbitrator for mapping logical addresses with physical block addresses, and for performing block management operations including: storing reassigned data to available blocks, relocating valid data in obsolete blocks to said available blocks and reassigning logical block addresses to physical block addresses of said available blocks, finding bad blocks of the flash memory device and replacing with reserve blocks, erasing obsolete blocks for recycling after relocating valid data to available blocks, and erase count wear leveling of blocks, etc. Furthermore, each flash memory device includes an internal buffer for accelerating the block management operations.

摘要翻译： 由主机可访问的电子数据闪存卡包括连接到闪速存储器件的闪存控制器和被激活以建立与主机的通信的输入 - 输出接口电路。 在一个实施例中，闪存卡使用USB接口电路与主机进行通信。 闪速存储器控制器包括用于将逻辑地址与物理块地址对准的仲裁器，并且用于执行块管理操作，包括：将重新分配的数据存储到可用块，将过时块中的有效数据重定位到所述可用块并将逻辑块地址重新分配给物理块地址 的所述可用块，找到闪存设备的坏块并用备用块替换，在将有效数据重新定位到可用块之后擦除用于再循环的废弃块，以及擦除块的计数损耗均衡等。此外，每个闪存设备包括 内部缓冲区，用于加快块管理操作。

公开(公告)号：US20070198856A1

公开(公告)日：2007-08-23

申请号：US11623863

申请日：2007-01-17

申请人： Charles Lee ,  I-Kang Yu ,  Edward Lee ,  Ming-Shiang Shen

发明人： Charles Lee ,  I-Kang Yu ,  Edward Lee ,  Ming-Shiang Shen

IPC分类号： G06F12/14

CPC分类号： G06F21/85 ,  G06F21/79

摘要： A secure flash-card reader reads a user ID from a secure card and finds a matching entry with a hashed password in a user table on the reader. An encrypted key is received from a secure host that hashes and encrypts a password the user types into the host and the user's ID. A card decryption engine uses a random number to decrypt the encrypted key and recover the hashed password and user ID from the secure host, which is compared by a comparator to the hashed password and user ID from the user table. A mismatch causes an access controller to block access to encrypted data on the secure card. Flash data is transferred over a flash-serial buffer bus between flash-card controllers and a RAM buffer. An encryption engine on the flash-serial buffer bus encrypts and decrypts data and connects to a serial engine to the host.

摘要翻译： 安全的闪存读卡器从安全卡读取用户ID，并在阅读器的用户表中找到具有散列密码的匹配条目。 从安全主机接收加密密钥，该密钥对用户键入的密码和用户的ID进行散列和加密。 卡解密引擎使用随机数来解密加密的密钥，并从安全主机中恢复散列密码和用户ID，由比较器与用户表中的散列密码和用户ID进行比较。 不匹配导致访问控制器阻止访问安全卡上的加密数据。 闪存数据通过闪存卡控制器和RAM缓冲区之间的闪存串行缓冲区总线进行传输。 闪存串行缓冲总线上的加密引擎加密和解密数据，并连接到主机的串行引擎。

公开(公告)号：US20080098164A1

公开(公告)日：2008-04-24

申请号：US11876251

申请日：2007-10-22

申请人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen

发明人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0866 ,  G06F2212/2022 ,  G06F2212/2515

摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The SRAM buffer also operates as a cache of flash data after booting is complete. Cache read and write hits use the SRAM cache rather than flash memory, while old cache lines and read misses access the flash memory. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory. The flash microcontroller uses a differential interface to the external host, with a differential transceiver and a differential serial interface. Frame, packet, and encoded clock processing is also performed by the serial interface.

摘要翻译： 闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。 引导完成后，SRAM缓冲区还可以作为闪存数据缓存。 缓存读取和写入命中使用SRAM缓存而不是闪存，而旧的缓存行和读取未命中访问闪存。 外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。 引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。 闪存单片机使用与外部主机的差分接口，具有差分收发器和差分串行接口。 帧，分组和编码时钟处理也由串行接口执行。

公开(公告)号：US20080071963A1

公开(公告)日：2008-03-20

申请号：US11979103

申请日：2007-10-31

申请人： David Chow ,  Sidney Young ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

发明人： David Chow ,  Sidney Young ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

IPC分类号： G06F13/20 ,  G06F12/02

CPC分类号： G06F13/409 ,  G06F2213/0026 ,  G06F2213/0042 ,  Y02D10/14 ,  Y02D10/151

摘要： An ExpressCard having USB connection has a card case having two opposite first and second end portions and two opposite lateral portions. A card connector is formed at the first end portion of the card case and having a USB interface. Flash chips are implemented in the card case. A USB flash controller implemented in the card case and connected between the USB interface and the flash chips in order to provide a data access to the flash chips through the USB interface. A USB socket, in form factors of Mini-USB or Extended Mini-connector-type, is implemented in the card case and connected to the USB flash controller in order to provide a data access to the one or more flash chips therethrough. An extended Universal-Serial Bus (EUSB) host enters a suspend mode rather than poll an ExpressCard that is busy performing a memory or other operation, thereby saving power.

摘要翻译： 具有USB连接的ExpressCard具有具有两个相对的第一和第二端部和两个相对的横向部分的卡盒。 卡连接器形成在卡盒的第一端部并且具有USB接口。 闪存芯片在卡盒中实现。 USB闪存控制器实现在卡盒中并连接在USB接口和闪存芯片之间，以通过USB接口提供对闪存芯片的数据访问。 一个USB插座，以Mini-USB或扩展迷你连接器类型的形式被实现在卡盒中并连接到USB闪存控制器，以便提供对一个或多个闪存芯片的数据访问。 扩展的通用串行总线（EUSB）主机进入挂起模式，而不是轮询正忙于执行内存或其他操作的ExpressCard，从而节省电量。

公开(公告)号：US20080065794A1

公开(公告)日：2008-03-13

申请号：US11928124

申请日：2007-10-30

申请人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

发明人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： An extended Universal-Serial Bus (EUSB) host has reduced loading by using radio frequency (RF) transceivers or direct wiring traces rather than a pair of legacy USB cables. The reduced loading opens the eye pattern. The EUSB device transfers internal data using chained Direct-Memory Access (DMA). Registers in a DMA controller point to a vector table that has vector entries, each pointing to a destination and a source. The source is a memory table for a memory group. The memory table has entries for several memory segments. Each memory-table entry has a pointer to a memory segment and a byte count for the segment. Once all bytes in the segment are transferred, a flag in the entry indicates when another memory segment follows within the memory group. When an END flag is read, then vector table is advanced to the next vector entry, and another memory group of memory segments processed.

摘要翻译： 扩展的通用串行总线（EUSB）主机通过使用射频（RF）收发器或直接布线轨迹而不是一对传统的USB电缆减少了负载。 减少负荷打开眼睛图案。 EUSB设备使用链接的直接内存访问（DMA）传输内部数据。 DMA控制器中的寄存器指向具有向量条目的向量表，每个向量表指向一个目的地和一个源。 源是内存组的内存表。 内存表有几个内存段的条目。 每个存储表条目具有指向存储器段的指针和段的字节计数。 一旦片段中的所有字节都被传送，该条目中的标志表示在存储器组中跟随其他内存段的时间。 读取END标志时，向量表前进到下一个向量条目，并处理另一个内存段的内存组。

公开(公告)号：US20080046608A1

公开(公告)日：2008-02-21

申请号：US11925933

申请日：2007-10-27

申请人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

发明人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

IPC分类号： G06F3/00

CPC分类号： G06F13/4045 ,  Y02D10/14 ,  Y02D10/151

摘要： An extended Universal-Serial Bus (EUSB) host enters a suspend mode rather than poll an EUSB device that is busy performing a memory or other operation. Power is saved since polling is avoided. The busy EUSB device sends a not-yet NYET signal back to the EUSB host to instruct the host to enter the suspend mode. When the EUSB device is ready to continue transfer with the host, the EUSB device wakes up the host by sending a ready RDY signal back to the host. The NYET and RDY signals may be tokens or flags in serial packets sent over a full-duplex connection to the host with two sets of differential pairs. Transfers may be re-started by the host after suspension once the requested data is read from flash memory, or space is made available in a sector buffer by completing earlier writes to flash memory.

摘要翻译： 扩展的通用串行总线（EUSB）主机进入暂停模式，而不是轮询正忙于执行内存或其他操作的EUSB设备。 省电，因为避免轮询。 繁忙的EUSB设备向EUSB主机发送一个尚未发送的NYET信号，指示主机进入挂起模式。 当EUSB设备准备好继续与主机进行传输时，EUSB设备通过将准备好的RDY信号发送回主机来唤醒主机。 NYET和RDY信号可以是通过全双工连接发送到具有两组差分对的主机的串行数据包中的令牌或标志。 一旦所请求的数据从闪存中读取，主机可以重新启动传输，或者通过完成对闪存的更早写入，在扇区缓冲器中可用空间。

公开(公告)号：US20070168614A1

公开(公告)日：2007-07-19

申请号：US11625310

申请日：2007-01-20

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  Ming-Shiang Shen

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F13/385

摘要： An adaptable-capacity Secure Digital (SD) card operates as a standard-capacity SD card for a standard-capacity SD 2.0 or 1.x host, and operates as a high-capacity SD card when connected to a high-capacity SD 2.0 host. A 32-bit argument received in a SD bus transaction from the host may be a 32-bit address, which can access 4 G bytes of flash memory in standard-capacity mode. For high-capacity mode, the addressable unit is a 512-byte sector, greatly increasing the addressable memory size. A SD protocol interface on a controller chip performs handshaking with the host to determine the SD version and memory capacity of the host. Host addresses are sent as byte or sector addresses to a flash memory manager on the controller chip, depending on the capacity mode agreed on during the handshaking. Memory areas on the adaptable-capacity SD card for high and standard modes can be separate or overlapping.

摘要翻译： 适用于容量的安全数字（SD）卡作为标准容量SD 2.0或1.x主机的标准容量SD卡运行，并连接到大容量SD 2.0主机时作为高容量SD卡运行 。 来自主机的SD总线事务中接收到的32位参数可以是32位地址，可以在标准容量模式下访问4 G字节的闪存。 对于高容量模式，可寻址单元是一个512字节的扇区，大大增加了可寻址的存储器大小。 控制器芯片上的SD协议接口与主机执行握手，以确定主机的SD版本和内存容量。 主机地址作为字节或扇区地址发送到控制器芯片上的闪存管理器，这取决于握手期间商定的容量模式。 适用于高容量SD卡的存储区域可以分开或重叠。

公开(公告)号：US20070147157A1

公开(公告)日：2007-06-28

申请号：US11625309

申请日：2007-01-20

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  Ming-Shiang Shen

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  Ming-Shiang Shen

IPC分类号： G11C5/14

CPC分类号： G11C5/143 ,  G11C5/147 ,  G11C16/30

摘要： A dual-voltage secure digital (SD) card can be inserted into a legacy host or a newer host. Legacy hosts drive a high voltage such as 3.3 volts onto the power line of the SD bus, while newer hosts drive the power line with a reduced voltage such as 1.8 volts. A flash and voltage controller chip on the SD card has a controller core that operates at the reduced voltage. A voltage regulator on the SD card, or a power management unit inside the controller chip generates an internal power voltage of 1.8 volts from the dual-voltage SD bus power line. The internal power voltage is applied to the controller core and to a voltage converter that generates a flash power voltage from the internal power voltage. The flash power voltage is applied to flash-memory chips on the SD card that operate at the higher voltage.

摘要翻译： 可以将双电压安全数字（SD）卡插入到旧式主机或更新的主机中。 传统主机将高压（例如3.3伏特）驱动到SD总线的电源线上，而较新的主机则以1.8伏特的降低电压驱动电源线。 SD卡上的闪存和电压控制器芯片具有以降低的电压工作的控制器核心。 SD卡上的电压调节器或控制器芯片内的电源管理单元从双电压SD总线电源线产生1.8伏特的内部电源电压。 内部电源电压被施加到控制器核心和电压转换器，其从内部电源电压产生闪光电源电压。 闪存电源电压被施加到在更高电压下工作的SD卡上的闪存芯片。

公开(公告)号：US20080034154A1

公开(公告)日：2008-02-07

申请号：US11871627

申请日：2007-10-12

申请人： Charles Lee ,  Abraham Ma ,  Frank Yu ,  David Chow ,  Ming-Shiang Shen

发明人： Charles Lee ,  Abraham Ma ,  Frank Yu ,  David Chow ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0607 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C16/0408 ,  G11C2211/5649

摘要： A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.

摘要翻译： 使用由物理顺序地址计数器生成的平面，块和页面地址从闪存中恢复RAM映射表。 RAM映射表在使用从逻辑块索引的最低位提取的交错比特的物理顺序地址计数器产生的平面交织序列之后恢复。 这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。 物理顺序地址计数器通过在中间物理块位之前递增平面交织比特，然后将MSB重定位到中间物理块比特之上来生成物理块号。 这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 还执行后台回收和ECC写入。

公开(公告)号：US20080034153A1

公开(公告)日：2008-02-07

申请号：US11871011

申请日：2007-10-11

申请人： Charles Lee ,  Frank Yu ,  Abraham Ma ,  David Chow ,  Ming-Shiang Shen

发明人： Charles Lee ,  Frank Yu ,  Abraham Ma ,  David Chow ,  Ming-Shiang Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0607 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C11/5621 ,  G11C16/0408

摘要： A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.

摘要翻译： PCIE总线上的闪存控制器控制闪存总线上的闪存模块。 闪存模块使用从逻辑块索引的最低位提取的交错比特进行平面交织。 这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。 物理顺序地址计数器通过在中间物理块比特之前递增平面交织比特，然后将MSB重新定位到中间物理块比特之上来生成物理块号。 这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 RAM物理页有效表跟踪四个平面中的有效页面，而RAM映射表存储由物理顺序地址计数器生成的逻辑扇区的平面，块和页面地址。