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    PREVENTING ISOLATION LEAKAGE IN III-V DEVICES
    53.
    发明申请
    PREVENTING ISOLATION LEAKAGE IN III-V DEVICES 有权
    防止III-V器件中的隔离泄漏

    公开(公告)号：US20140001519A1

    公开(公告)日：2014-01-02

    申请号：US13538985

    申请日：2012-06-29

    申请人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

    发明人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

    IPC分类号： H01L29/78 ,  H01L21/762

    CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/785

    摘要： A fin is formed over a first barrier layer over a substrate. The first barrier layer has a band gap greater than the band gap of the fin. In one embodiment, a gate dielectric layer is deposited on the top surface and opposing sidewalls of the fin and is adjacent to a second barrier layer deposited on the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin and an isolating layer is formed adjacent to the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin, and an isolating layer is formed adjacent to the second barrier layer deposited between the fin and the first barrier layer.

    摘要翻译： 翅片形成在衬底上的第一阻挡层上。 第一阻挡层的带隙大于翅片的带隙。 在一个实施例中，栅极电介质层沉积在鳍的顶表面和相对侧壁上，并且与沉积在鳍下方的第一阻挡层上的第二势垒层相邻。 在一个实施例中，栅极电介质层沉积在顶表面上，翅片的相对的侧壁和隔离层邻近鳍片下方的第一阻挡层形成。 在一个实施例中，栅极电介质层沉积在鳍的顶表面和相对侧壁上，隔离层形成在沉积在鳍与第一阻挡层之间的第二势垒层附近。

    TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TO INTEGRATED CIRCUIT DEVICES
    54.
    发明申请
    TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TO INTEGRATED CIRCUIT DEVICES 有权
    对集成电路设备进行驱动的技术和配置

    公开(公告)号：US20110147706A1

    公开(公告)日：2011-06-23

    申请号：US12646697

    申请日：2009-12-23

    申请人： Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

    发明人： Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

    IPC分类号： H01L29/778 ,  H01L21/335

    CPC分类号： H01L29/7782 ,  B82Y10/00 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848

    摘要： Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a first barrier layer coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier layer, the quantum well channel comprising a first material having a first lattice constant, and a source structure coupled to the quantum well channel, the source structure comprising a second material having a second lattice constant, wherein the second lattice constant is different than the first lattice constant to impart a strain on the quantum well channel. Other embodiments may be described and/or claimed.

    摘要翻译： 本公开的实施例描述了为诸如水平场效应晶体管等集成电路器件施加应变的技术和配置。 集成电路器件包括半导体衬底，与半导体衬底耦合的第一势垒层，耦合到第一势垒层的量子阱沟道，量子阱沟道包括具有第一晶格常数的第一材料和耦合到 量子阱沟道，源结构包括具有第二晶格常数的第二材料，其中第二晶格常数不同于在量子阱沟道上施加应变的第一晶格常数。 可以描述和/或要求保护其他实施例。

    TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TO INTEGRATED CIRCUIT DEVICES
    59.
    发明申请
    TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TO INTEGRATED CIRCUIT DEVICES 审中-公开
    对集成电路设备进行驱动的技术和配置

    公开(公告)号：US20140103294A1

    公开(公告)日：2014-04-17

    申请号：US14106556

    申请日：2013-12-13

    申请人： Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

    发明人： Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

    IPC分类号： H01L29/778 ,  H01L29/66

    CPC分类号： H01L29/7782 ,  B82Y10/00 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848

    摘要： Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a quantum well channel coupled with the semiconductor substrate, a source structure coupled with the quantum well channel, a drain structure coupled with the quantum well channel and a strain-inducing film disposed on and in direct contact with material of the source structure and the drain structure to reduce resistance of the quantum well channel by imparting a tensile or compressive strain on the quantum well channel, wherein the quantum well channel is disposed between the strain-inducing film and the semiconductor substrate. Other embodiments may be described and/or claimed.

    摘要翻译： 本公开的实施例描述了为诸如水平场效应晶体管等集成电路器件施加应变的技术和配置。 集成电路器件包括半导体衬底，与半导体衬底耦合的量子阱沟道，与量子阱沟道耦合的源极结构，与量子阱沟道耦合的漏极结构以及直接接触的应变诱导膜 其中源结构和漏极结构的材料通过在量子阱沟道上施加拉伸或压缩应变来降低量子阱沟道的电阻，其中量子阱沟道设置在应变诱导膜和半导体衬底之间。 可以描述和/或要求保护其他实施例。