公开(公告)号：US20170005176A1

公开(公告)日：2017-01-05

申请号：US15100262

申请日：2013-12-27

申请人： SEUNG HOON SUNG ,  ROBERT B. TURKOT, JR. ,  ANAND S. MURTHY ,  SEIYON KIM ,  KELIN J. KUHN

发明人： SEUNG HOON SUNG ,  ROBERT B. TURKOT, JR. ,  ANAND S. MURTHY ,  SEIYON KIM ,  KELIN J. KUHN

IPC分类号： H01L29/66 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/67 ,  H01L29/423

CPC分类号： H01L29/6681 ,  H01L21/3065 ,  H01L21/67069 ,  H01L29/0673 ,  H01L29/42392

摘要： The present disclosure relates to a method of etching sacrificial material. The method includes supplying a semiconductor substrate in a reaction chamber, wherein the substrate includes a channel disposed on the substrate and a sacrificial layer disposed on at least a portion of the channel. The method further includes supplying an interhalogen vapor to the reaction chamber, etching at least a portion of the sacrificial layer with the interhalogen vapor and exposing at least a portion of said channel from under the sacrificial layer.

摘要翻译： 本公开涉及一种蚀刻牺牲材料的方法。 该方法包括在反应室中提供半导体衬底，其中衬底包括设置在衬底上的沟道和设置在沟道的至少一部分上的牺牲层。 所述方法还包括向所述反应室提供卤间蒸气，用所述卤素蒸气蚀刻所述牺牲层的至少一部分并且从所述牺牲层下面暴露所述通道的至少一部分。

公开(公告)号：US20140170998A1

公开(公告)日：2014-06-19

申请号：US13720852

申请日：2012-12-19

申请人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Robert S. CHAU

发明人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Robert S. CHAU

IPC分类号： H01L29/80 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

摘要： A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

公开(公告)号：US20140091361A1

公开(公告)日：2014-04-03

申请号：US13631417

申请日：2012-09-28

申请人： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

发明人： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

摘要： An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

公开(公告)号：US20130071297A1

公开(公告)日：2013-03-21

申请号：US13527842

申请日：2012-06-20

申请人： J. Gary Eden ,  Sung-Jin Park ,  Jin Hoon Cho ,  Seung Hoon Sung ,  Min Hwan Kim

发明人： J. Gary Eden ,  Sung-Jin Park ,  Jin Hoon Cho ,  Seung Hoon Sung ,  Min Hwan Kim

IPC分类号： H01J37/32 ,  C25D11/02

CPC分类号： B01J19/0093 ,  B01J2219/00783 ,  B01J2219/00842 ,  B01J2219/00853 ,  B01J2219/00891 ,  C01B13/115 ,  C25D11/02 ,  C25D11/022 ,  C25D11/026 ,  C25D11/12 ,  C25D11/18 ,  C25D11/26 ,  H01J11/18 ,  H01J11/22 ,  H01J11/34 ,  H01J17/066 ,  H01J17/16 ,  H01J37/32055 ,  H05H2001/2412 ,  H05H2001/2418

摘要： A microplasma device includes a microcavity or microchannel defined at least partially within a thick metal oxide layer consisting essentially of defect free oxide. Electrodes are arranged with respect to the microcavity or microchannel to stimulate plasma generation in said microcavity or microchannel. At least one of the electrodes is encapsulated within the thick metal oxide layer. A method of fabricating a microcavity or microchannel plasma device includes anodizing a flat or gently curved or gently sloped metal substrate to form a thick layer of metal oxide consisting essentially of nanopores that are perpendicular to the surface of the metal substrate. Material removal is conducted to remove metal oxide material to form a microcavity or microchannel in the thick layer of metal oxide.

摘要翻译： 微型装置包括至少部分地在基本上由无缺陷氧化物组成的厚金属氧化物层内限定的微腔或微通道。 电极相对于微腔或微通道布置以刺激所述微腔或微通道中的血浆产生。 至少一个电极被封装在厚的金属氧化物层内。 一种制造微腔或微通道等离子体装置的方法包括阳极氧化平坦或轻柔地弯曲或缓慢倾斜的金属基底，以形成基本上由纳米孔组成的厚层，金属氧化物垂直于金属基底的表面。 进行材料去除以除去金属氧化物材料以在金属氧化物的厚层中形成微腔或微通道。

公开(公告)号：US20100072893A1

公开(公告)日：2010-03-25

申请号：US12235796

申请日：2008-09-23

申请人： J. Gary Eden ,  Sung-Jin Park ,  Seung Hoon Sung

发明人： J. Gary Eden ,  Sung-Jin Park ,  Seung Hoon Sung

IPC分类号： H01J17/49 ,  H01J9/24

CPC分类号： H01J65/046 ,  H01J9/241 ,  H01J11/18

摘要： The invention provides microcavity plasma devices and arrays that are formed in layers that also seal the plasma medium, i.e., gas(es) and/or vapors. No separate packaging layers are required and additional packaging can be omitted if it is desirable to do so. A preferred microcavity plasma device includes first and second thin layers that are joined together. A half ellipsoid microcavity or plurality of half ellipsoid microcavities is defined in one or both of the first and second thin layers, and electrodes are arranged with respect to the microcavity to excite a plasma within said microcavities upon application of a predetermined voltage to the electrodes. A method for forming a microcavity plasma device having a plurality of half or full ellipsoid microcavities in one or both of first and second thin layers is also provided by a preferred embodiment. The method includes defining a pattern of protective polymer on the first thin layer. Powder blasting forms half ellipsoid microcavities in the first thin layer. The second thin layer is joined to the first layer. The patterning can be conducted lithographically or can be conduced with a simple screen.

摘要翻译： 本发明提供了形成为也密封等离子体介质即气体和/或蒸汽的层的微腔等离子体装置和阵列。 不需要单独的包装层，如果要这样做，可以省略额外的包装。 优选的微腔等离子体装置包括连接在一起的第一和第二薄层。 半椭圆形微腔或多个半椭圆形微腔被限定在第一和第二薄层中的一个或两个中，并且相对于微腔布置电极，以在对电极施加预定电压时在所述微腔内激发等离子体。 优选实施例也提供了一种在第一和第二薄层中的一个或两个中形成具有多个半或全椭圆形微腔的微腔等离子体装置的方法。 该方法包括在第一薄层上限定保护性聚合物的图案。 粉末喷射在第一薄层中形成半椭圆形微腔。 第二薄层连接到第一层。 图案化可以光刻地进行，或者可以用简单的屏幕进行。

公开(公告)号：US20200098875A1

公开(公告)日：2020-03-26

申请号：US16142036

申请日：2018-09-26

申请人： Seung Hoon SUNG ,  Justin WEBER ,  Matthew METZ ,  Arnab SEN GUPTA ,  Abhishek SHARMA ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Charles KUO ,  Nazila HARATIPOUR ,  Shriram SHIVARAMAN ,  Van H. LE ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Sean MA

发明人： Seung Hoon SUNG ,  Justin WEBER ,  Matthew METZ ,  Arnab SEN GUPTA ,  Abhishek SHARMA ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Charles KUO ,  Nazila HARATIPOUR ,  Shriram SHIVARAMAN ,  Van H. LE ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Sean MA

IPC分类号： H01L29/417 ,  H01L29/08 ,  H01L29/205 ,  H01L29/49 ,  H01L29/45 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L27/108 ,  H01L29/267

摘要： Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20160204276A1

公开(公告)日：2016-07-14

申请号：US14912403

申请日：2013-09-25

申请人： Sansaptak DASGUPTA ,  Han Wui THEN ,  Sanaz GARDNER ,  Benjamin CHU-KUNG ,  Marko RADOSAVLJEVIC ,  Seung Hoon SUNG ,  Robert CHAU

发明人： Sansaptak DASGUPTA ,  Han Wui THEN ,  Sanaz GARDNER ,  Benjamin CHU-KUNG ,  Marko RADOSAVLJEVIC ,  Seung Hoon SUNG ,  Robert CHAU

IPC分类号： H01L29/786 ,  H01L29/04 ,  H01L29/51 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L27/108 ,  H01L29/06

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02516 ,  H01L21/0254 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/2003 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7786 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78618 ,  H01L29/78681

摘要： Methods of forming high voltage (111) silicon nano-structures are described. Those methods and structures may include forming a III-V device layer on (111) surface of a silicon fin structure, forming a 2DEG inducing polarization layer on the III-V device layer, forming a source/drain material on a portion of the III-V device layer on terminal ends of the silicon fin. A middle portion of the silicon fin structure between the source and drain regions may be removed, and backfilled with a dielectric material, and then a gate dielectric and a gate material may be formed on the III-V device layer.

摘要翻译： 描述了形成高电压（111）硅纳米结构的方法。 这些方法和结构可以包括在硅鳍结构的（111）表面上形成III-V器件层，在III-V器件层上形成2DEG诱导极化层，在III部分上形成源极/漏极材料 -V在硅片末端的器件层。 源极和漏极区域之间的硅鳍结构的中间部分可以被去除，并且用电介质材料回填，然后可以在III-V器件层上形成栅极电介质和栅极材料。

公开(公告)号：US09136343B2

公开(公告)日：2015-09-15

申请号：US13749139

申请日：2013-01-24

申请人： Ravi Pillarisetty ,  Willy Rachmady ,  Van H. Le ,  Seung Hoon Sung ,  Jessica S. Kachian ,  Jack T. Kavalieros ,  Han Wui Then ,  Gilbert Dewey ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Niloy Mukherjee

发明人： Ravi Pillarisetty ,  Willy Rachmady ,  Van H. Le ,  Seung Hoon Sung ,  Jessica S. Kachian ,  Jack T. Kavalieros ,  Han Wui Then ,  Gilbert Dewey ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78609 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

摘要： Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

摘要翻译： 描述具有锗或III-V族有源层的深栅极全面半导体器件。 例如，非平面半导体器件包括设置在衬底上的异质结构。 异质结构包括不同组成的上层和下层之间的异质结。 有源层设置在杂结构上方，并且具有与异质结构的上层和下层不同的组成。 栅电极堆叠设置在有源层的沟道区上并完全包围有源层的沟道区，并且设置在上层中的沟槽中，并且至少部分地设置在异质结构的下层中。 源极和漏极区域设置在栅电极堆叠的任一侧上的有源层和上层中，而不是在下层中。

公开(公告)号：US08954021B2

公开(公告)日：2015-02-10

申请号：US14303513

申请日：2014-06-12

申请人： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sanaz Gardner ,  Seung Hoon Sung ,  Robert S. Chau

发明人： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sanaz Gardner ,  Seung Hoon Sung ,  Robert S. Chau

IPC分类号： H04B1/04 ,  H01L29/772 ,  H01L29/20 ,  H01L29/80 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

摘要： A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

摘要翻译： III-N半导体沟道形成在形成于诸如翅片侧壁的硅模板结构的（111）或（110）表面上的III-N过渡层上。 在实施例中，硅鳍具有与更适应的种子层的III-N外延膜厚度相当的宽度，允许更低的缺陷密度和/或降低的外延膜厚度。 在实施例中，过渡层是GaN，并且半导体沟道包括铟（In）以增加从硅片的导带偏移。 在其它实施例中，鳍是牺牲性的，并且在晶体管制造期间被去除或氧化，或以其它方式转换为电介质结构。 在采用牺牲散热片的某些实施例中，III-N过渡层和半导体通道是基本上纯的GaN，允许击穿电压高于在硅片存在时可持续的击穿电压。

公开(公告)号：US08896101B2

公开(公告)日：2014-11-25

申请号：US13725546

申请日：2012-12-21

申请人： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Robert S. Chau

发明人： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Robert S. Chau

IPC分类号： H01L29/20 ,  H01L29/772 ,  H01L29/66

CPC分类号： H01L29/78696 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/02538 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66409 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78681

摘要： A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

摘要翻译： III-N半导体通道在过渡层和III-N偏振层之间组成分级。 在实施例中，栅堆叠沉积在包括渐变III-N半导体沟道的鳍的侧壁上，允许在响应于栅极偏置电压的至少两个侧壁表面相邻的III-N半导体沟道中形成传输沟道。 在实施例中，栅极叠层完全沉积在包括III-N半导体沟道的纳米线周围，该纳米线被组成分级，以使得能够响应于栅极形成与偏振层和过渡层两者相邻的III-N半导体沟道中的传输沟道 偏压。