公开(公告)号：US06687883B2

公开(公告)日：2004-02-03

申请号：US09750969

申请日：2000-12-28

申请人： John M. Cohn ,  Alvar A. Dean ,  David J. Hathaway ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Alvar A. Dean ,  David J. Hathaway ,  Sebastian T. Ventrone

IPC分类号： G06F1750

CPC分类号： G06F1/3243 ,  G06F1/3203 ,  Y02D10/152 ,  Y02D50/20

摘要： A method for reducing leakage power of a logic network comprising the steps of: using (observability) don't care information to identify “sleep states” for individual nets; determining based on probabilistic analysis at least one net in which expected power consumption will be reduced by forcing a net to a particular value during at least a portion of a “sleep state”; and forcing the determined net to the determined value determined portion of that “sleep state”.

摘要翻译： 一种用于减少逻辑网络的泄漏功率的方法，包括以下步骤：使用（可观察性）不关心信息以识别各个网络的“睡眠状态”; 基于概率分析确定至少一个网络，其中通过在“睡眠状态”的至少一部分期间将网络强制为特定值来减少预期功率消耗; 并将所确定的网络强制为所述“睡眠状态”的确定值确定部分。

公开(公告)号：US20120124534A1

公开(公告)日：2012-05-17

申请号：US12944059

申请日：2010-11-11

申请人： Kerim Kalafala ,  Jennifer E. Basile ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Peihua Qi ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

发明人： Kerim Kalafala ,  Jennifer E. Basile ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Peihua Qi ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/504 ,  G06F2217/84

摘要： A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack.

摘要翻译： 一种在断言到达时间之间的相关性存在的静态时序分析中应用公共路径信用的方法，包括以下步骤：使用计算机识别存在一个或多个相关性的一个或多个断言到达时间对; 将所述一个或多个断言到达时间对中的每一个传播到取决于所述一个或多个相关性的定时值; 以及对至少一个测试执行随后的公共路径悲观消除分析，在该测试期间，使用取决于所述到达时间之间的一个或多个相关性的定时值来计算经调整的测试松弛。

公开(公告)号：US07743355B2

公开(公告)日：2010-06-22

申请号：US11942034

申请日：2007-11-19

申请人： Jun Zhou ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Patrick M. Williams

发明人： Jun Zhou ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Patrick M. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F2217/84

摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

摘要翻译： 公开了一种用于提高大型，复杂，高性能数字集成电路闭合的效率和有效性的方法。 电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。 改善次临界信号时序的动机是信号临界性的递减函数。 因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

公开(公告)号：US07669156B2

公开(公告)日：2010-02-23

申请号：US12014138

申请日：2008-01-15

申请人： David J. Hathaway ,  Kerim Kalafala

发明人： David J. Hathaway ,  Kerim Kalafala

IPC分类号： G06F17/50

CPC分类号： H04L41/14 ,  H04L43/0852 ,  H04L43/16

摘要： A method of performing node-based static timing analysis on a digital network and a program storage device for implementing the method, wherein the method comprises partitioning timing delays in the digital network into portions attributable to a factor of interest and portions attributable to other factors; multiplying the timing delays by different weights based on the factor of interest to produce weighted timing delays; and using the multiplied timing delays to determine a relative impact of the factor of interest on the various paths in the digital network. The method further comprises setting arrival times of timing signals at digital network path start points to zero and identifying digital network paths whose timing delays are dominated by a particular factor of interest. The different weights comprise any of a positive weight, a negative weight, and a zero weight.

摘要翻译： 一种在数字网络上执行基于节点的静态时序分析的方法和用于实现该方法的程序存储设备，其中该方法包括将数字网络中的定时延迟分成可归因于其他因素的关注因素和部分; 基于感兴趣的因素将定时延迟乘以不同的权重以产生加权定时延迟; 并且使用相乘的定时延迟来确定感兴趣因素对数字网络中各种路径的相对影响。 该方法还包括将数字网络路径起点处的定时信号的到达时间设置为零，并且识别其定时延迟由特定感兴趣的因素支配的数字网络路径。 不同的重量包括正重量，负重量和零重量中的任何一种。

公开(公告)号：US07650246B2

公开(公告)日：2010-01-19

申请号：US11162200

申请日：2005-08-31

申请人： Harry J. Beatty, III ,  David J. Hathaway ,  Alexander J. Suess

发明人： Harry J. Beatty, III ,  David J. Hathaway ,  Alexander J. Suess

IPC分类号： G01R15/00 ,  G06F19/00

CPC分类号： G01R31/31725

摘要： A method and device for determining a delay of a gate driven by a driving gate with different ground or supply voltages. The method includes determining from the supply and ground voltages for the driven gate and its driving gate an adjusted supply voltage value, and applying the adjusted supply voltage value as a single voltage parameter to a pre-characterized delay model for the driven gate. The device is structured to perform the method.

摘要翻译： 一种用于确定由具有不同接地或电源电压的驱动门驱动的栅极的延迟的方法和装置。 该方法包括从驱动栅极及其驱动栅极的电源和地电压确定经调整的电源电压值，并将调整的电源电压值作为单个电压参数应用于驱动栅极的预定义延迟模型。 该设备的结构是执行该方法。

公开(公告)号：US20080263488A1

公开(公告)日：2008-10-23

申请号：US11737289

申请日：2007-04-19

申请人： Revanta Banerji ,  David J. Hathaway ,  Alex Rubin ,  Alexander J. Suess

发明人： Revanta Banerji ,  David J. Hathaway ,  Alex Rubin ,  Alexander J. Suess

IPC分类号： G06F17/50 ,  H03H11/26

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control elements within the clock distribution network. The method provides a total solution to the skew scheduling problem by way of a two-phase iterative process. The two phases of the process alternately keep track of the schedule generated by first taking the gating elements of the clock distribution network into account, followed by balancing any remaining skew that may exist on the memory elements of the same clock distribution network. Finally, the method describes a procedure to post-process the skew schedule to ensure that it can be implemented using a clock tree generation tool.

摘要翻译： 用于产生时钟分配网络的偏斜调度的方法产生考虑时钟分配网络的端点处的存储器元件的定时要求以及提供时钟门和其它时钟控制的门控信号的定时要求的调度 时钟分配网络中的元素。 该方法通过两阶段迭代过程为偏斜调度问题提供了一个完整的解决方案。 该过程的两个阶段交替地跟踪通过首先考虑时钟分配网络的门控元件产生的调度，然后平衡可能存在于相同时钟分配网络的存储器元件上的任何剩余的偏移。 最后，该方法描述了用于后处理偏斜调度以确保可以使用时钟树生成工具来实现的过程。

公开(公告)号：US20080250279A1

公开(公告)日：2008-10-09

申请号：US11696981

申请日：2007-04-05

申请人： Gary D. Grise ,  David J. Hathaway ,  Vikram Iyengar

发明人： Gary D. Grise ,  David J. Hathaway ,  Vikram Iyengar

IPC分类号： G01R31/28

CPC分类号： G01R31/31715 ,  G01R31/31707 ,  G01R31/318328

摘要： A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as “exercised.” Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently.

摘要翻译： 一种使用自动测试图案生成工具自动生成数字逻辑电路测试图案的方法。 该方法包括生成测试模式并将故障行为应用于数字逻辑电路内的各种路径。 随着每个电路路径的测试，沿电路路径的测试电路节点被标记为“行使”。 通过避免标记的电路节点组装后续测试路径。 以这种方式，可以增加测试路径的覆盖范围，并且可以有效地测试许多电路节点。

公开(公告)号：US07404163B2

公开(公告)日：2008-07-22

申请号：US11277385

申请日：2006-03-24

申请人： Thomas B. Chadwick, Jr. ,  Margaret R. Charlebois ,  David J. Hathaway ,  Jason E. Rotella ,  Douglas W. Stout ,  Ivan L. Wemple

发明人： Thomas B. Chadwick, Jr. ,  Margaret R. Charlebois ,  David J. Hathaway ,  Jason E. Rotella ,  Douglas W. Stout ,  Ivan L. Wemple

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

摘要翻译： 公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。 在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。 瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。 使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

公开(公告)号：US20080172638A1

公开(公告)日：2008-07-17

申请号：US11623122

申请日：2007-01-15

申请人： Michael S. Gray ,  David J. Hathaway ,  Jason D. Hibbeler ,  Robert F. Walker ,  Xin Yuan

发明人： Michael S. Gray ,  David J. Hathaway ,  Jason D. Hibbeler ,  Robert F. Walker ,  Xin Yuan

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method of optimizing hierarchical very large scale integration (VLSI) design by use of cluster-based cell cloning. The method of the present invention provides improved yield or migration by reusing cells in order to reduce the number of unique instances of at least one of the reused cells. The method performs hierarchal optimization on the reduced set of clones (i.e., clusters). The method of the present disclosure includes, but is not limited to, the steps of setting the initial clustering parameters; assembling the physical design from existing reused cells; for each cell type, performing a full cloning operation in order to create a full set of duplicate cells; for each cell type, performing a full optimization of the design; for each cell type, performing an analyses of all cell environments and performing a clustering operation; and analyzing the overall results in order to determine whether the optimization objectives are achieved.

摘要翻译： 通过使用基于簇的细胞克隆来优化分级超大规模集成（VLSI）设计的方法。 本发明的方法通过重新使用细胞来提供改善的产量或迁移，以减少至少一个重复使用的细胞的唯一实例的数量。 该方法对减少的克隆集合（即，簇）执行层次优化。 本公开的方法包括但不限于设置初始聚类参数的步骤; 从现有的重复使用的电池组装物理设计; 对于每个单元格类型，执行完全克隆操作以便创建一整套重复的单元格; 对于每个单元格类型，执行设计的全面优化; 对于每个单元类型，执行所有单元环境的分析并执行聚类操作; 并分析总体结果，以确定是否实现优化目标。

公开(公告)号：US07117466B2

公开(公告)日：2006-10-03

申请号：US10665273

申请日：2003-09-18

申请人： Kerim Kalafala ,  Peihua Qi ,  David J. Hathaway ,  Alexander J. Suess ,  Chandramouli Visweswariah

发明人： Kerim Kalafala ,  Peihua Qi ,  David J. Hathaway ,  Alexander J. Suess ,  Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account. Based on a specified target slack, each failing timing test is examined to determine a consistent set of parameter settings which produces the worst possible slack. The analysis is performed on a path basis. By considering only parameters which are in common to a particular data/clock path-pair, the number of process combinations that need to be explored is reduced when compared to analyzing all combinations of the global parameter settings. Further, if parameters are separable and linear, worst-case variable assignments for a particular clock/data path pair can be computed in linear time by independently assigning each parameter value. In addition, if available, the incremental delay change with respect to each physically realizable process variable may be used to project the worst-case variable assignment on a per-path basis without the need for performing explicit corner enumeration.

摘要翻译： 描述了静态时序分析中消除悲观情绪的方法。 延迟表示为离散参数设置的函数，允许将本地和全局变量都用于账户。 根据指定的目标松弛，检查每个失败的定时测试，以确定一组一致的参数设置，从而产生最差的松弛。 分析以路径为基础进行。 通过仅考虑与特定数据/时钟路径对共同的参数，与分析全局参数设置的所有组合相比，需要探索的进程组合的数量减少。 此外，如果参数是可分离的和线性的，则通过独立地分配每个参数值，可以在线性时间内计算特定时钟/数据路径对的最差情况变量分配。 另外，如果可用，可以使用相对于每个物理上可实现的过程变量的增量延迟变化来在每个路径基础上投射最坏情况的变量赋值，而不需要执行明确的角点枚举。