公开(公告)号：US20100290567A1

公开(公告)日：2010-11-18

申请号：US12844451

申请日：2010-07-27

申请人： Giuseppe VISALLI ,  Francesco Pappalardo

发明人： Giuseppe VISALLI ,  Francesco Pappalardo

IPC分类号： H04L27/06 ,  H03M7/40

CPC分类号： H04L12/2856

摘要： Embodiment for forming an aggregate signal from a plurality of starting signals, comprising:acquiring said starting signals through respective sensors of a homogeneous sensors group;converting acquired signals in respective digital signals having data represented with a predetermined bits number;processing the digital signals to form aggregate signal.The processing step comprises the operations of:modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data;forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.

摘要翻译： 用于从多个起始信号形成聚集信号的实施例，包括：通过均匀传感器组的相应传感器获取所述起始信号; 在具有以预定比特数表示的数据的各个数字信号中转换获取的信号; 处理数字信号以形成聚合信号。 处理步骤包括以下操作：修改将每个这样的数字信号的数据格式从第一格式改变为第二格式的数字信号，第二格式中的每个数据是从第一格式的相应数据获得的， 根据与所述数据相关联的置换方案和包括该数据的特定数字信号来排列比特位置; 形成通过对所述修改的数字信号相应数据作用的按位逻辑运算器获得所述聚合信号数据的聚合信号。

公开(公告)号：US20100289628A1

公开(公告)日：2010-11-18

申请号：US12844460

申请日：2010-07-27

申请人： Giuseppe Visalli ,  Francesco Pappalardo

发明人： Giuseppe Visalli ,  Francesco Pappalardo

IPC分类号： G08B9/00

CPC分类号： H04L12/2856

摘要： Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.

公开(公告)号：US07447716B2

公开(公告)日：2008-11-04

申请号：US11018972

申请日：2004-12-21

申请人： Francesco Pappalardo ,  Agatino Pennisi

发明人： Francesco Pappalardo ,  Agatino Pennisi

IPC分类号： G06F5/00

CPC分类号： G06F9/30025 ,  G06F1/3203 ,  Y10S707/99955

摘要： The method of coding data within a data processing unit includes a representation as twos-complement and a coded representation of the data. The coded representation is a semi-negated representation. A data processing unit includes a memory device connected bidirectionally to a data bus, itself connected to a processing architecture which includes at least one arithmetic-logic unit. Advantageously, the data processing unit includes at least one data coding/decoding block connected between the processing architecture and the data bus.

摘要翻译： 在数据处理单元内编码数据的方法包括作为二进制补码和数据的编码表示的表示。 编码表示是半正负表示。 数据处理单元包括双向连接到数据总线的存储器件，数据总线本身连接到包括至少一个算术逻辑单元的处理架构。 有利地，数据处理单元包括连接在处理架构和数据总线之间的至少一个数据编码/解码块。

公开(公告)号：US07372916B2

公开(公告)日：2008-05-13

申请号：US10670993

申请日：2003-09-25

申请人： Francesco Pappalardo ,  Giuseppe Notarangelo

发明人： Francesco Pappalardo ,  Giuseppe Notarangelo

IPC分类号： H04L27/00

CPC分类号： G06F13/4072 ,  G06F13/4213

摘要： Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.

摘要翻译： 数字信号在给定时刻的总线上以非编码格式和编码格式有选择地发送。 基于在上述给定时刻的总线上发送的信号与总线上的信号发送器的比较，部分地采用以非编码格式或编码格式发送信号的决定 在前一时刻，以便最小化总线上的开关活动。

公开(公告)号：US07358868B2

公开(公告)日：2008-04-15

申请号：US10757368

申请日：2004-01-13

申请人： Francesco Pappalardo ,  Agatino Pennisi

发明人： Francesco Pappalardo ,  Agatino Pennisi

IPC分类号： H03M5/00

CPC分类号： G06F13/423 ,  Y02D10/14 ,  Y02D10/151

摘要： N binary signals are transmitted through a bus of m leads, where m

摘要翻译： 通过在第二信号上编码第一信号，以一串时钟脉冲的节奏通过m个引线的总线m

公开(公告)号：US07333470B2

公开(公告)日：2008-02-19

申请号：US10841414

申请日：2004-05-07

申请人： Francesco Rimi ,  Giuseppe Avellone ,  Francesco Pappalardo ,  Agostino Galluzzo

发明人： Francesco Rimi ,  Giuseppe Avellone ,  Francesco Pappalardo ,  Agostino Galluzzo

IPC分类号： H04J3/06

CPC分类号： H04B1/70735 ,  H04B1/7083 ,  H04B2201/70702 ,  H04B2201/70707

摘要： To execute the cell-search procedure in a cellular communication system (such as a system based upon the 3GPP TDD standard), there are available identification codes for the second step (slot synchronization) and for the third step (identification of the scrambling codes). The identification codes are identified by a process of correlation with the received signal and are used for obtaining from a correspondence table the parameters for the execution of the second step (CD) or of the third step (SCR). The correspondence table is stored in a reduced form by the identification, according to rules of symmetry and redundancy, of subtables designed to generate the entire table by appropriate combination operations. The search procedure in the correspondence table thus reduced is conveniently modified by the introduction of the combination operations. A preferential application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95 or WBCDMA.

摘要翻译： 为了在蜂窝通信系统（例如基于3GPP TDD标准的系统）中执行小区搜索过程，存在用于第二步骤（时隙同步）和第三步骤（识别扰码）的可用识别码， 。 通过与接收信号相关的处理来识别识别码，并且用于从对应表获得执行第二步骤（CD）或第三步骤（SCR）的参数。 根据对称规则和冗余度，通过适当组合操作生成整个表格的子表的标识，缩小形式存储对应表。 通过引入组合操作可以方便地修改由此减少的对应表中的搜索过程。 基于诸如UMTS，CDMA2000，IS95或WBCDMA的标准的移动通信系统中的优先应用。

公开(公告)号：US07289426B2

公开(公告)日：2007-10-30

申请号：US10669167

申请日：2003-09-23

申请人： Francesco Pappalardo ,  Daniele Lo Iacono ,  Giuseppe Avellone ,  Agostino Galluzzo

发明人： Francesco Pappalardo ,  Daniele Lo Iacono ,  Giuseppe Avellone ,  Agostino Galluzzo

IPC分类号： H04J11/00

CPC分类号： H04J13/0044 ,  H04J13/12

摘要： Described herein is a method for parallel generating Walsh-Hadamard (WH) channelization codes and Orthogonal Variable Spreading Factor (OVSF) channelization codes, which are channelization codes formed by a plurality of strings of antipodal digits, each having a given length L and being identifiable by respective indices I formed by strings of binary digits, each having a given length N equal to the logarithm in base two of the length L of the channelization codes, the antipodal digits of the channelization codes assuming the values +1 and −1 and the binary digits of said indices I assuming the values 0 and 1. The method according to the invention enables determination of the antipodal digits of the channelization codes according to the binary digits of the corresponding indices I, implementing specific EXOR logic operations, by means of which there are first generated intermediate binary digits, which are then encoded with the antipodal digits of the channelization codes using an encoding criterion according to which the intermediate binary digits 0 and 1 can be encoded, respectively, with the antipodal digits −1 and +1 or else with the antipodal digits +1 and −1 according to the type of binary encoding chosen a priori for the antipodal digits themselves.

摘要翻译： 这里描述了一种用于并行生成沃尔什 - 哈达玛（WH）信道化码和正交可变扩频因子（OVSF）信道化码的方法，它们是由多个对数字串组成的信道化码，每个字符串具有给定的长度L并且是可识别的 通过由二进制数字串形成的各自的索引I，每一个二进制数字的每一个具有等于信道化码的长度L的基本二的对数的给定长度N，假定值+1和-1的信道化码的对数位和 假定值0和1的所述索引I的二进制数字。根据本发明的方法能够根据对应索引I的二进制数字来确定信道化码的对数位，实现特定的EXOR逻辑运算，借此， 有第一个生成的中间二进制数字，然后使用相邻的编码与信道化代码的对数位数 ding标准，根据该标准，中间二进制数字0和1可以分别编码为对数位数-1和+1，或者根据根据先前选择的二进制编码的类型编码反对数字+1和-1 对数字本身

公开(公告)号：US07191314B2

公开(公告)日：2007-03-13

申请号：US10682378

申请日：2003-10-09

申请人： Francesco Pappalardo ,  Agatino Pennisi

发明人： Francesco Pappalardo ,  Agatino Pennisi

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/30076 ,  G06F9/30181 ,  G06F9/3897

摘要： A reconfigurable control structure for CPUs comprises a first control unit with a first basic instruction set associated therewith, and a second control unit, with a second instruction set associated therewith. Associated with the second control unit is at least one programming element for rendering the second instruction set selectively modifiable. Also present is at least one circuit element for supplying instruction codes to be executed to the first control unit and to the second control unit, so that each instruction can be executed under the control of at least one between the first control unit or the second control unit according to whether the instruction is comprised in the first basic instruction set and/or in the second selectively modifiable instruction set.

摘要翻译： 用于CPU的可重构控制结构包括具有与其相关联的第一基本指令集的第一控制单元和具有与其相关联的第二指令集的第二控制单元。 与第二控制单元相关联的是用于使第二指令集可选择地修改的至少一个编程元件。 还存在用于向第一控制单元和第二控制单元提供要执行的指令代码的至少一个电路元件，使得每个指令可以在第一控制单元或第二控制器之间的至少一个的控制下执行 根据指令是否包含在第一基本指令集和/或第二可选择修改的指令集中的单元。

公开(公告)号：US20050283587A1

公开(公告)日：2005-12-22

申请号：US11145780

申请日：2005-06-06

申请人： Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elena Salurso

发明人： Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elena Salurso

IPC分类号： G06F1/32 ,  G06F15/00 ,  G06F15/80

CPC分类号： G06F15/8023 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/3885 ,  G06F9/3887 ,  Y02D10/171 ,  Y02D50/20

摘要： A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able to receive the same input signals. The number of associated processing elements is selectively variable in the direction of the column so as to exploit the parallelism of said signals. The architecture can be scaled in various dimensions in an optimal configuration for the algorithm to be executed.

摘要翻译： 处理器架构包括用于处理输入信号的多个处理元件。 该架构根据包括行和列的矩阵来组织，其列包括至少一个具有计算部分的微处理器块和能够接收相同输入信号的一组相关联的处理元件。 相关联的处理元件的数量在列的方向上选择性地变化，以便利用所述信号的并行性。 该架构可以在要执行的算法的最佳配置中以各种尺寸缩放。

公开(公告)号：US20050281562A1

公开(公告)日：2005-12-22

申请号：US10963737

申请日：2004-10-12

申请人： Francesco Pappalardo ,  Giuseppe Notarangelo ,  Giuseppe Visalli

发明人： Francesco Pappalardo ,  Giuseppe Notarangelo ,  Giuseppe Visalli

IPC分类号： H04B10/50 ,  H04B10/516 ,  H04B10/80 ,  H04L25/49 ,  H04B10/04

CPC分类号： H04B10/5055 ,  H04B10/503 ,  H04B10/516 ,  H04B10/801 ,  H04L25/4915

摘要： A method for transmitting on an optical connection an input data sequence having first and second logic states, includes encoding the input data sequence prior to transmission on the optical connection, where the encoding minimizes the first logic states in the encoded data sequence. The encoding includes: arranging the input data sequence in parallel on a number of bus lines; counting the first logic states in the input data sequence; comparing the counting result with a value equal to half of the lines; and logically inverting the input data sequence on the lines if the counting result is greater than half of the lines of the input data sequence. The method further includes: ordering values of the input data sequence; identifying the first value having the first logic state; and applying the encoding operation just to the ordered values subsequent to the first value having the first logic state.

摘要翻译： 一种用于在光学连接上传送具有第一和第二逻辑状态的输入数据序列的方法，包括在光学连接上传输之前对输入数据序列进行编码，其中编码使编码数据序列中的第一逻辑状态最小化。 编码包括：在多条总线上并行布置输入数据序列; 对输入数据序列中的第一逻辑状态进行计数; 将计数结果与等于一半行的值进行比较; 并且如果计数结果大于输入数据序列的行的一半，则对行上的输入数据序列进行逻辑反相。 该方法还包括：排序输入数据序列的值; 识别具有第一逻辑状态的第一值; 以及将所述编码操作恰好应用于具有所述第一逻辑状态的所述第一值之后的有序值。