公开(公告)号：US10438955B2

公开(公告)日：2019-10-08

申请号：US15995896

申请日：2018-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/768 ,  H01L27/11 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L23/535

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one of a portion of the hard masks; forming sacrificial pillars over the substrate; forming sacrificial gates, wherein at least one sacrificial gate contacts at least one sacrificial pillar; growing an epitaxial layer between the at least one sacrificial gate and the at least one sacrificial pillar; starting a RMG process on the sacrificial gates; etching to remove the sacrificial pillars and form pillar openings; and completing the RMG process to fill the pillar openings and the gate openings with a metal.

公开(公告)号：US10290654B2

公开(公告)日：2019-05-14

申请号：US15160623

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Min-hwa Chi

IPC: H01L27/12 ,  H01L27/092 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/11 ,  H01L21/8234

Abstract: Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor.

公开(公告)号：US10269811B2

公开(公告)日：2019-04-23

申请号：US16114596

申请日：2018-08-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min-hwa Chi ,  Hui Zang

IPC: H01L27/11 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/108 ,  H01L23/535 ,  H01L29/45 ,  H01L29/66

Abstract: FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality of source/drain regions within the substrate adjacent to each of the gates; a dielectric disposed between each gate and the plurality of source/drain regions adjacent to each gate; a dielectric capping layer disposed on a first one of the at least two gates, wherein no dielectric capping layer is disposed on a second one of the at least two gates; and a local interconnect electrically connected to the second one of the at least two gates, wherein the dielectric capping layer disposed on the first one of the at least two gates prevents an electrical connection between the local interconnect and the first one of the at least two gates.

公开(公告)号：US10170353B2

公开(公告)日：2019-01-01

申请号：US15634091

申请日：2017-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/74 ,  H01L23/48 ,  H01L29/06 ,  H01L29/10 ,  H01L21/762 ,  H01L21/768

Abstract: Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method includes, for instance: obtaining a wafer with a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; and forming at least one opening having sidewalls and a bottom surface within the filled at least one recess. An intermediate semiconductor device is also disclosed.

公开(公告)号：US10056468B2

公开(公告)日：2018-08-21

申请号：US15258333

申请日：2016-09-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srikanth Balaji Samavedan ,  Manfred Eller ,  Min-hwa Chi ,  Hui Zang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance. The resulting semiconductor structure includes a semiconductor substrate with fin(s) thereon, FinFET(s) integral with the fin(s), the FinFET(s) including a gate electrode, a gate liner lining the gate electrode, and air-gap(s) in gate trench(es) of the FinFET(s), reducing parasitic capacitance by at least about 75 percent as compared to no air-gaps.

公开(公告)号：US09916903B2

公开(公告)日：2018-03-13

申请号：US14514289

申请日：2014-10-14

Applicant: GlobalFoundries Inc.

Inventor： Akhilesh Gautam ,  Suresh Uppal ,  Min-hwa Chi

IPC: G11C17/12 ,  H01L27/112 ,  G11C17/18

CPC classification number: G11C17/12 ,  G11C17/18 ,  H01L27/11233

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

公开(公告)号：US09905673B2

公开(公告)日：2018-02-27

申请号：US15620082

申请日：2017-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen-Pin Peng ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/225

CPC classification number: H01L29/66636 ,  H01L21/2253 ,  H01L21/26506 ,  H01L29/6659 ,  H01L29/7847 ,  H01L29/7848

Abstract: Disclosed are methods for stress memorization techniques. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.

公开(公告)号：US09865603B2

公开(公告)日：2018-01-09

申请号：US14662734

申请日：2015-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L27/11 ,  H01L21/82 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/092 ,  H01L27/0924

Abstract: A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.

公开(公告)号：US09812393B2

公开(公告)日：2017-11-07

申请号：US14867341

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Suraj K. Patil ,  Min-hwa Chi

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L23/5226

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

公开(公告)号：US09704759B2

公开(公告)日：2017-07-11

申请号：US14845543

申请日：2015-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen Pin Peng ,  Min-hwa Chi ,  Garo Jacques Derderian

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/823864 ,  H01L21/0206 ,  H01L21/02252 ,  H01L21/0234 ,  H01L21/31111 ,  H01L21/823814 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/78

Abstract: Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.