公开(公告)号：US20180151238A1

公开(公告)日：2018-05-31

申请号：US15881356

申请日：2018-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Suresh Uppal ,  Min-hwa Chi

IPC: G11C17/12 ,  H01L27/112 ,  G11C17/18

CPC classification number: G11C17/12 ,  G11C17/18 ,  H01L27/11233

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

公开(公告)号：US09601187B1

公开(公告)日：2017-03-21

申请号：US15046983

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/06

CPC classification number: G11C29/56 ,  G11C7/04 ,  G11C8/08 ,  G11C11/418

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device yield and/or reliability through bias temperature instability (BTI). One device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line controls access to each pass gate of a first number of cells; a word line driver electrically connected to each word line; and a control line configured to provide an operational write voltage or a first write voltage to each word line through the word line driver. By virtue of BTI, application of the first write voltage may lead to improved stability of data desired to be read from one or more cells of the device.

公开(公告)号：US10147496B2

公开(公告)日：2018-12-04

申请号：US15881356

申请日：2018-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Suresh Uppal ,  Min-hwa Chi

IPC: G11C17/12 ,  G11C17/18 ,  H01L27/112

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

公开(公告)号：US10068660B2

公开(公告)日：2018-09-04

申请号：US15615660

申请日：2017-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G11C29/00 ,  G11C29/52 ,  G11C11/419 ,  G11C11/412

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS through the array VCS driver.

公开(公告)号：US20160104541A1

公开(公告)日：2016-04-14

申请号：US14514289

申请日：2014-10-14

Applicant: GlobalFoundries Inc.

Inventor： Akhilesh Gautam ,  Suresh Uppal ,  Min-hwa Chi

IPC: G11C17/12 ,  G11C17/18

CPC classification number: G11C17/12 ,  G11C17/18 ,  H01L27/11233

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

Abstract translation: 所公开的至少一种方法，装置和系统涉及将数据硬编码到集成电路装置中。 提供集成电路装置。 接收到集成电路装置的一部分的硬布线信息的数据。 应力电压信号被提供给集成电路器件的晶体管的一部分，用于引起晶体管部分的电介质击穿以硬接线数据。

公开(公告)号：US20170242759A1

公开(公告)日：2017-08-24

申请号：US15047395

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G06F11/16 ,  G06F11/20

CPC classification number: G06F11/167 ,  G06F11/2015 ,  G06F2201/85 ,  G11C7/04 ,  G11C11/419 ,  G11C29/00 ,  G11C29/028 ,  G11C29/52

Abstract: Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.

公开(公告)号：US09704600B1

公开(公告)日：2017-07-11

申请号：US15047271

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G11C11/00 ,  G11C29/52 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C29/52 ,  G11C7/04 ,  G11C11/412 ,  G11C11/419

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS through the array VCS driver.

公开(公告)号：US09916212B2

公开(公告)日：2018-03-13

申请号：US15047395

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/20

CPC classification number: G06F11/167 ,  G06F11/2015 ,  G06F2201/85 ,  G11C7/04 ,  G11C11/419 ,  G11C29/00 ,  G11C29/028 ,  G11C29/52

Abstract: Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.

公开(公告)号：US09601188B1

公开(公告)日：2017-03-21

申请号：US15047139

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Randy W. Mann ,  William McMahon ,  Yoann Mamy Randriamihaja ,  Yuncheng Song

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C29/70 ,  G11C7/04 ,  G11C8/08 ,  G11C11/418 ,  G11C29/56

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device yield and/or reliability through bias temperature instability (BTI). One device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line controls access to each pass gate of a first number of cells; a word line driver electrically connected to each word line; a row decoder configured to authorize or deauthorize a write voltage to each word line through the word line driver, wherein the write voltage is selected from an operational write voltage or a first write voltage; and a control line configured to provide an operational write voltage or a first write voltage to each word line authorized by the row decoder, wherein the first write voltage is greater than an operational write voltage.

公开(公告)号：US09460806B2

公开(公告)日：2016-10-04

申请号：US14680228

申请日：2015-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Akhilesh Gautam ,  Suresh Uppal

IPC: H01L27/112 ,  H01L21/66 ,  G11C17/12 ,  G01R31/26

CPC classification number: G11C17/12 ,  G01R31/26 ,  H01L22/34 ,  H01L27/11206 ,  H01L29/205

Abstract: A method of forming an OTPROM capable of storing twice the number of bits as a conventional OTPROM without increasing the overall size of the device is provided. Embodiments include forming a OTPROM, the OTPROM array having a plurality of formed devices; receiving a binary code to program the OTPROM array; separating the binary code into a first part and a second part; programming each device with one of four data storage states by: forming a gate oxide layer of each device to a thickness corresponding to the first part of the binary code, and selectively applying a TDDB stress to the gate oxide layer corresponding to the second part of the binary code; detecting a Idsat level discharged by each device with a multi-bit sense amplifier; and reading the state of each device based on the detected Idsat level.

Abstract translation: 提供了一种形成能够存储两倍于常规OTPROM的位数的OTPROM的方法，而不增加设备的总体大小。 实施例包括形成OTPROM，OTPROM阵列具有多个形成的器件; 接收二进制代码来编程OTPROM阵列; 将二进制代码分离成第一部分和第二部分; 通过以下方式对每个器件进行编程：通过以下方式对每个器件进行编程：将每个器件的栅极氧化层形成为与二进制代码的第一部分对应的厚度，并且选择性地将TDDB应力施加到对应于第二部分的栅极氧化物层 二进制代码; 用多位读出放大器检测每个器件放电的Idsat电平; 并且基于检测到的Idsat级别读取每个设备的状态。