公开(公告)号：US08413029B2

公开(公告)日：2013-04-02

申请号：US12402359

申请日：2009-03-11

申请人： Richard Rauschmayer ,  Hongwei Song

发明人： Richard Rauschmayer ,  Hongwei Song

IPC分类号： H03M13/03 ,  G11C29/00

CPC分类号： G11B20/1803 ,  G11B20/1816 ,  G11C29/028 ,  G11C29/42 ,  G11C2029/0411 ,  H03M13/1102

摘要： Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed.

摘要翻译： 本文描述的方法和结构提供了用于调整LDPC纠错码的纠错能力。 例如，一个实施例的系统包括适于对已经用LDPC纠错码编码的数据进行解码的解码器。 该系统还包括通信地耦合到解码器并且适于在解码器解码之前估计数据中的位值的检测器。 检测器还适于基于比特值估计改变比特值，以减少LDPC纠错码的纠错能力。 误差校正能力的降低是可调节的，从而可以逐渐分析存储设备的扇区故障率。

公开(公告)号：US20130050005A1

公开(公告)日：2013-02-28

申请号：US13215815

申请日：2011-08-23

申请人： Jingfeng Liu ,  Nayak Ratnakar Aravind ,  Hongwei Song ,  Haotian Zhang

发明人： Jingfeng Liu ,  Nayak Ratnakar Aravind ,  Hongwei Song ,  Haotian Zhang

IPC分类号： H03M1/12

CPC分类号： H04L25/067 ,  G11B20/10037 ,  H03H17/04 ,  H03H17/06 ,  H03H21/0012 ,  H03H2017/0247 ,  H03H2017/0297

摘要： Methods and apparatus are provided for processing a signal in a read channel using a selective oversampled analog to digital conversion. The disclosed selective oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain. An oversampled analog to digital conversion is applied to an analog input signal to generate a plurality of digital samples for a given bit interval. The plurality of digital samples for a given bit interval are applied to a corresponding plurality of data detectors to obtain a detected output. The plurality of digital samples for a given bit interval may have a phase offset relative to one another. The detected output may be obtained, for example, by summing the outputs of the plurality of data detectors or by aggregating weighted outputs of the plurality of data detectors.

摘要翻译： 提供了用于使用选择性过采样模数转换处理读通道中的信号的方法和装置。 所公开的选择性过采样模数转换通过将均衡和/或滤波处理的至少一部分转移到数字域来简化了模拟设计。 将过采样的模数转换应用于模拟输入信号，以产生给定位间隔的多个数字采样。 将给定位间隔的多个数字样本应用于相应的多个数据检测器以获得检测到的输出。 给定比特间隔的多个数字样本可以具有相对于彼此的相位偏移。 检测的输出可以例如通过对多个数据检测器的输出求和或者通过聚合多个数据检测器的加权输出来获得。

公开(公告)号：US08315132B1

公开(公告)日：2012-11-20

申请号：US13235658

申请日：2011-09-19

申请人： Shaohua Yang ,  Hongwei Song ,  Zining Wu ,  Xueshi Yang ,  Hongxin Song

发明人： Shaohua Yang ,  Hongwei Song ,  Zining Wu ,  Xueshi Yang ,  Hongxin Song

IPC分类号： G11B15/52

CPC分类号： G11B20/10009 ,  G11B20/10046 ,  G11B20/10296 ,  G11B20/1816

摘要： A system and method are provided to detect defects in a data storage medium by sampling data read from the data storage medium. Time referenced samples of data read from the data storage medium are equalized to mediate the effects of channel noise and the equalized samples are decoded by a decoder, such as a Viterbi decoder. The decoded signal is then reconstructed through a reconstruction filter to approximate the equalized signal. The equalized data signal and the reconstructed data signal are then combined and compared in a bit-by-bit deconstruction scheme to determine, based on a variation between the signal elements, that a defect exists on the data storage medium. Additional action is then taken to mediate the effects of attempting to process corrupted data based on the defect by isolating the defective bit.

摘要翻译： 提供了一种系统和方法，用于通过对从数据存储介质读取的数据进行采样来检测数据存储介质中的缺陷。 将从数据存储介质读取的数据的时间参考样本相等以调解信道噪声的影响，并且均衡样本由诸如维特比解码器之类的解码器解码。 然后通过重建滤波器重建经解码的信号以近似均衡的信号。 然后将均衡的数据信号和重建的数据信号以逐位解构方案进行组合和比较，以基于信号元素之间的变化来确定数据存储介质上存在缺陷。 然后采取额外的行动来通过隔离有缺陷的位来调解基于缺陷来处理被破坏的数据的效果。

公开(公告)号：US20120236430A1

公开(公告)日：2012-09-20

申请号：US13050129

申请日：2011-03-17

申请人： Weijun Tan ,  Hongwei Song ,  Kelly Fitzpatrick

发明人： Weijun Tan ,  Hongwei Song ,  Kelly Fitzpatrick

IPC分类号： G11B5/09

CPC分类号： G11B20/10379 ,  G11B20/10314 ,  G11B20/10472 ,  G11B2220/2516 ,  H03M13/1111 ,  H03M13/6331 ,  H03M13/6343 ,  H03M13/658

摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit having a data detection circuit is disclosed that includes: a scaling circuit, a soft output calculation circuit, and a factor calculation circuit. The scaling circuit is operable to scale a branch metric value by a scaling factor to yield a scaled output. The soft output calculation circuit is operable to calculate a soft output based at least in part on the scaled output. The factor calculation circuit operable to modify the scaling factor based at least in part on the soft output.

摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例，公开了具有数据检测电路的数据处理电路，其包括：缩放电路，软输出计算电路和因子计算电路。 缩放电路可操作以通过缩放因子缩放分支度量值以产生缩放的输出。 软输出计算电路可操作以至少部分地基于缩放的输出来计算软输出。 因子计算电路可操作以至少部分地基于软输出来修改缩放因子。

公开(公告)号：US08266505B2

公开(公告)日：2012-09-11

申请号：US12540283

申请日：2009-08-12

申请人： Jingfeng Liu ,  Hongwei Song

发明人： Jingfeng Liu ,  Hongwei Song

IPC分类号： H03M13/00

CPC分类号： G06F3/05 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/27 ,  H03M13/3905 ,  H03M13/41 ,  H03M13/47 ,  H03M13/63 ,  H03M13/6331

摘要： Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. The offline timing loop interpolates a derivative of the first series of data samples to yield a second series of data samples that mimics a series of data samples corresponding to the analog input that were sampled using a free running clock. The second series of data samples is interpolated to adjust each bit in accordance with an average frequency offset exhibited across the second series of data samples.

摘要翻译： 本发明的各种实施例提供了用于数据处理系统的系统和方法。 作为一个示例，描述了包括模数转换器，在线定时循环和离线定时循环的数据处理电路。 模数转换器接收模拟输入并提供第一系列数据样本第一系列数据采样的每一位对应于在更新的采样时钟控制的时间的模拟输入。 在线定时循环至少部分地基于第一系列数据样本的处理版本来修改更新的采样时钟。 离线时序循环内插第一系列数据样本的导数，以产生模拟与使用自由运行时钟采样的模拟输入相对应的一系列数据样本的第二系列数据采样。 根据在第二系列数据样本中显示的平均频率偏移，内插第二系列数据样本以调整每个位。

公开(公告)号：US08219892B2

公开(公告)日：2012-07-10

申请号：US12399713

申请日：2009-03-06

申请人： Weijun Tan ,  Hongwei Song ,  Shaohua Yang

发明人： Weijun Tan ,  Hongwei Song ,  Shaohua Yang

IPC分类号： G06F11/00

CPC分类号： G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10055 ,  H03M13/3905

摘要： Various embodiments of the present invention provide systems and methods for detecting storage medium defects. As one example, a media defect detection system is disclosed that includes a data detector circuit that applies a detection algorithm to the data input and provides a hard output and a soft output. A first circuit combines a first derivative of the hard output with a derivative of the data input to yield a first combined signal. A second circuit combines a second derivative of the hard output with a derivative of the first combined signal to yield a second combined signal. A third circuit combines a derivative of the soft output with the second combined signal and a threshold value to yield a defect signal.

摘要翻译： 本发明的各种实施例提供了用于检测存储介质缺陷的系统和方法。 作为一个示例，公开了一种媒体缺陷检测系统，其包括将检测算法应用于数据输入并提供硬输出和软输出的数据检测器电路。 第一电路将硬输出的一阶导数与数据输入的导数组合以产生第一组合信号。 第二电路将硬输出的二阶导数与第一组合信号的导数组合以产生第二组合信号。 第三电路将软输出的导数与第二组合信号和阈值组合以产生缺陷信号。

公开(公告)号：US08201051B2

公开(公告)日：2012-06-12

申请号：US12287959

申请日：2008-10-15

申请人： Weijun Tan ,  Shaohua Yang ,  Hongwei Song

发明人： Weijun Tan ,  Shaohua Yang ,  Hongwei Song

IPC分类号： H03M13/00

CPC分类号： H03M13/1128 ,  H03M13/17

摘要： The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gate is operable for receiving the first signal vial the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors.

摘要翻译： 本发明是用于检测短脉冲串错误的装置。 该设备包括第一信号输入，其中第一信号输入被配置为接收第一信号。 该设备包括第二信号输入，其中第二信号输入被配置为接收第二信号。 该装置包括逻辑门，其中逻辑门可操作用于接收第一信号输入端，第一信号输入端，经由第二信号输入端接收第二信号，并根据接收到的第一信号和第二信号产生逻辑输出门信号 信号。 此外，该器件包括滤波器，其中滤波器被配置为从逻辑门接收逻辑输出门信号，并且基于接收的逻辑输出门信号产生滤波器输出信号，其中滤波器输出信号可用于标记误差。

公开(公告)号：US20110298543A1

公开(公告)日：2011-12-08

申请号：US12792555

申请日：2010-06-02

申请人： Jingfeng Liu ,  Hongwei Song

发明人： Jingfeng Liu ,  Hongwei Song

IPC分类号： H03G3/20

CPC分类号： G11B20/10009 ,  G11B20/10027 ,  G11B20/10462 ,  G11B2020/1287 ,  G11B2220/2516 ,  H03G1/0088

摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier, a gain circuit, and hybrid gain feedback combination circuit. The variable gain amplifier is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The gain circuit is operable to calculate a first algorithm error component and a second algorithm error component based at least in part on the amplified output. The hybrid gain feedback combination circuit is operable combine the first algorithm error component and the second algorithm error component to yield the gain feedback value when the data input includes a synchronization pattern.

摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，本发明的一些实施例提供包括可变增益放大器，增益电路和混合增益反馈组合电路的数据处理电路。 可变增益放大器可操作以将增益应用于对应于增益反馈值的数据输入并提供放大的输出。 增益电路可操作以至少部分地基于放大的输出来计算第一算法误差分量和第二算法误差分量。 当数据输入包括同步模式时，混合增益反馈组合电路可操作地组合第一算法误差分量和第二算法误差分量以产生增益反馈值。

公开(公告)号：US20100185906A1

公开(公告)日：2010-07-22

申请号：US12402359

申请日：2009-03-11

申请人： Richard Rauschmayer ,  Hongwei Song

发明人： Richard Rauschmayer ,  Hongwei Song

IPC分类号： G11C29/04 ,  H03M13/35 ,  G06F11/10 ,  G06F11/22

CPC分类号： G11B20/1803 ,  G11B20/1816 ,  G11C29/028 ,  G11C29/42 ,  G11C2029/0411 ,  H03M13/1102

摘要： Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed.

摘要翻译： 本文描述的方法和结构提供了用于调整LDPC纠错码的纠错能力。 例如，一个实施例的系统包括适于对已经用LDPC纠错码编码的数据进行解码的解码器。 该系统还包括通信地耦合到解码器并且适于在解码器解码之前估计数据中的位值的检测器。 检测器还适于基于比特值估计改变比特值，以减少LDPC纠错码的纠错能力。 误差校正能力的降低是可调节的，从而可以逐渐分析存储设备的扇区故障率。

公开(公告)号：US20090276689A1

公开(公告)日：2009-11-05

申请号：US12380237

申请日：2009-02-25

申请人： Weijun Tan ,  Shaohua Yang ,  Hongwei Song

发明人： Weijun Tan ,  Shaohua Yang ,  Hongwei Song

IPC分类号： G06F11/07

CPC分类号： H03M13/27 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/2957 ,  H03M13/2987 ,  H03M13/3746 ,  H03M13/3905 ,  H03M13/4146 ,  H03M13/6331 ,  H03M13/6337

摘要： A system, method, and device for detecting short burst errors in a queue-based system is disclosed. A first detector performs a data detection on a first input data set at a first time and on a second input data set at a second time. A second detector performs a data re-detection on input data sets. A decoder decodes derivations of the outputs of the first and second detector. A short burst error detector may perform a short burst error detection on decoded data and erase any detected errors. An output data buffer stores and orders the decoded data for output.

摘要翻译： 公开了一种用于检测基于队列的系统中的短脉冲串错误的系统，方法和装置。 第一检测器在第一时间对第一输入数据集合和第二输入数据集进行数据检测。 第二检测器对输入数据集执行数据重新检测。 解码器解码第一和第二检测器的输出的导数。 短脉冲串错误检测器可对解码数据执行短脉冲串错误检测，并擦除任何检测到的错误。 输出数据缓冲器存储并排序解码数据进行输出。