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公开(公告)号：US06535429B2
公开(公告)日：2003-03-18
申请号：US10028747
申请日：2001-12-20
IPC分类号： G11C1606
CPC分类号： G11C16/28
摘要： A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.
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公开(公告)号：US06288960B1
公开(公告)日：2001-09-11
申请号：US09686326
申请日：2000-10-11
IPC分类号： G11C700
摘要： A bias circuit for read amplifier circuits for memories includes at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors includes a P-channel diode connected transistor and an N-channel transistor connected in series, with an enable transistor interposed therebetween. The first circuit branch drives a capacitive load for coupling to the supply voltage. The bias circuit further includes reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch for charging the capacitive load. A circuit portion, which controls the charging current of the capacitive load, includes a feedback loop between the reference current amplifier circuit branches and the capacitive load.
摘要翻译： 用于存储器的读取放大器电路的偏置电路包括由连接在电源电压和地之间的第一对MOS晶体管形成的至少一个第一电路支路。 第一对MOS晶体管包括串联连接的P沟道二极管晶体管和N沟道晶体管，其间插入有使能晶体管。 第一个电路分支驱动电容性负载以耦合到电源电压。 偏置电路还包括用于放大在第一电路支路中流动以对电容性负载充电的参考电流的参考电流放大器电路分支。 控制电容性负载的充电电流的电路部分包括参考电流放大器电路分支和容性负载之间的反馈回路。
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公开(公告)号：US08704588B2
公开(公告)日：2014-04-22
申请号：US12913658
申请日：2010-10-27
CPC分类号： G05F3/30 , H03F3/347 , H03F3/45183 , H03F2203/45466
摘要： A bandgap voltage reference circuit for generating a bandgap voltage reference. An embodiment comprises a current generator controlled by a first driving voltage for generating a first current depending on the driving voltage, and a first reference circuit element coupled to the controlled current generator for receiving the first current and generating a first reference voltage in response to the first current. The circuit further comprises a second reference circuit element for receiving a second current corresponding to the first current; said second reference circuit element is adapted to generate a second reference voltage in response to the second current. The circuit further comprises an operational amplifier having a first input coupled to the first circuit element and a second input coupled to the second reference circuit element. The circuit also comprises a control circuit comprising first capacitive element and second capacitive element.
摘要翻译： 一种用于产生带隙电压基准的带隙电压参考电路。 一个实施例包括由第一驱动电压控制的电流发生器，用于根据驱动电压产生第一电流，以及耦合到受控电流发生器的第一参考电路元件，用于接收第一电流并响应于第一电压产生第一参考电压 第一流。 电路还包括用于接收对应于第一电流的第二电流的第二参考电路元件; 所述第二参考电路元件适于响应于第二电流产生第二参考电压。 电路还包括具有耦合到第一电路元件的第一输入和耦合到第二参考电路元件的第二输入的运算放大器。 该电路还包括一个包括第一电容元件和第二电容元件的控制电路。
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公开(公告)号：US08587360B2
公开(公告)日：2013-11-19
申请号：US13435262
申请日：2012-03-30
IPC分类号： H03L5/00
CPC分类号： H03K17/102 , H03K3/356113
摘要： A level-shifter circuit may include a pair of inputs which receive a first and a second low-voltage phase signal having a first voltage dynamic with a first maximum value. The level-shifter circuit may also include a pair of outputs which supply a first high-voltage phase signal and a second high-voltage phase signal, level-shifted with respect to the low-voltage signals and having a second voltage dynamic with a second maximum value, higher than the first maximum value. The level-shifter circuit may further include transfer transistors coupled between one of a first reference terminal and a second reference terminal, which are set at one of a first reference voltage and a second reference voltage, and the first output or second output. Protection elements may be coupled to a respective transfer transistor to protect from overvoltages between at least one of the corresponding conduction terminals and control terminals.
摘要翻译： 电平移动器电路可以包括一对输入，其接收具有第一最大值的具有第一电压动态的第一和第二低电压相位信号。 电平移位器电路还可以包括一对输出，其提供相对于低电压信号电平移位的第一高电压相位信号和第二高电压相位信号，并且具有第二电压动态的第二高电压相位信号 最大值，高于第一个最大值。 电平移位器电路还可以包括耦合在第一参考端子和第二参考端子之一中的传输晶体管，其被设置为第一参考电压和第二参考电压之一以及第一输出或第二输出。 保护元件可以耦合到相应的传输晶体管，以防止在相应的导电端子和控制端子中的至少一个之间的过电压。
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55.发明申请公开(公告)号：US20120274393A1
公开(公告)日：2012-11-01
申请号：US13435210
申请日：2012-03-30
IPC分类号： G05F3/10
CPC分类号： H03K17/102 , H03K3/356113
摘要： A biasing circuit may include an input configured to receive a supply voltage, a value of which is higher than a limit voltage. The biasing circuit may also include a control stage configured to generate first and second control signals with mutually complementary values, equal alternatively to a first value, in a first half-period of a clock signal, or to a second value, in a second half-period of the clock signal. The first and second values may be a function of the supply and limit voltages. The biasing circuit may also include a biasing stage configured to generate a biasing voltage as a function of the values of the first and second control signals. The first and second control signals may control transfer transistors for transferring the supply voltage to respective outputs, while the biasing voltage may be for controlling protection transistors to reduce overvoltages on the transfer transistors.
摘要翻译： 偏置电路可以包括被配置为接收其值高于限制电压的电源电压的输入。 偏置电路还可以包括控制级，其被配置为在时钟信号的第一半个周期中产生第二和第二控制信号，该第一和第二控制信号具有相互互补的值，等于第一个值，或在第二个半个时钟信号中的第二个值 时钟信号的周期。 第一和第二值可以是电源和极限电压的函数。 偏置电路还可以包括被配置为产生作为第一和第二控制信号的值的函数的偏置电压的偏置级。 第一和第二控制信号可以控制用于将电源电压传送到各个输出的转移晶体管，而偏置电压可以用于控制保护晶体管以减小转移晶体管的过电压。
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56.发明授权Non-volatile memory including an auxiliary memory area with rotating sectors 有权非易失性存储器包括具有旋转扇区的辅助存储区域公开(公告)号：US08050107B2
公开(公告)日：2011-11-01
申请号：US12113721
申请日：2008-05-01
申请人： Francesco La Rosa , Antonino Conte
发明人： Francesco La Rosa , Antonino Conte
IPC分类号： G11C16/04
CPC分类号： G11C16/225 , G11C16/102
摘要： A method writes data in a non-volatile memory. The method provides, in the memory, a non-volatile main memory area comprising target pages, a non-volatile auxiliary memory area comprising auxiliary pages, and, in the auxiliary memory area: a current sector comprising erased auxiliary pages usable to write data, a save sector comprising auxiliary pages comprising data linked to target pages to be erased or being erased, a transfer sector comprising auxiliary pages including data to be transferred to erased target pages, and an unavailable sector comprising auxiliary pages to be erased or being erased. The method can be applied in particular to FLASH memories.
摘要翻译： 一种方法将数据写入非易失性存储器。 该方法在存储器中提供包括目标页面的非易失性主存储器区域，包括辅助页面的非易失性辅助存储器区域，并且在辅助存储器区域中：包括可用于写入数据的擦除辅助页面的当前扇区， 包括辅助页面的保存扇区，包括链接到要擦除或被擦除的目标页面的数据，包括辅助页面的传送扇区，包括要传送到已擦除的目标页面的数据，以及包括要被擦除或被擦除的辅助页面的不可用扇区。 该方法可以特别地应用于闪速存储器。
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公开(公告)号：US07791953B2
公开(公告)日：2010-09-07
申请号：US12113692
申请日：2008-05-01
申请人： Francesco La Rosa , Antonino Conte
发明人： Francesco La Rosa , Antonino Conte
IPC分类号： G11C16/04
CPC分类号： G11C16/225 , G11C16/102
摘要： A method writes data in a non-volatile memory comprising a main memory area comprising target locations, and an auxiliary memory area comprising auxiliary locations. The method comprises a write-erase cycle comprising: reading an initial set of data in a source location located in the main or auxiliary memory area; inserting the piece of data to be written into the initial set of data, to obtain an updated set of data, partially erasing a first group of auxiliary locations and a group of target locations designated by locations of a second group of auxiliary locations, and writing, in an erased auxiliary location of a third group of auxiliary locations, the updated set of data and the address of the target location. The method is particularly applicable to FLASH memories.
摘要翻译： 一种方法将数据写入非易失性存储器，包括包括目标位置的主存储区域和包括辅助位置的辅助存储区域。 该方法包括写擦除周期，包括：在位于主或辅助存储器区域的源位置读取初始数据集; 将要写入的数据片段插入到初始数据集中，以获得更新的数据集，部分地擦除辅助位置的第一组和由第二组辅助位置的位置指定的一组目标位置，以及写入 在第三组辅助位置的擦除辅助位置中，更新的数据集和目标位置的地址。 该方法特别适用于闪速存储器。
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公开(公告)号：US07551041B2
公开(公告)日：2009-06-23
申请号：US11261395
申请日：2005-10-28
IPC分类号： H03K3/02
CPC分类号： H03K3/0231
摘要： An oscillator is provided that includes at least one capacitor, at least one comparator, and at least one device for charging or discharging the at least one capacitor. The capacitor is coupled to the comparator. The comparator compares the voltage on the capacitor with a reference voltage, and activates the device so as to command the charging or the discharging of the capacitor. The oscillator also comprises a circuit for supplying a preset voltage to the comparator when the device commands the charging of the capacitor, so that the comparator compares the reference voltage diminished by the preset voltage with the voltage on the capacitor, or the voltage on the capacitor added to the preset voltage with the reference voltage.
摘要翻译： 提供了一种振荡器，其包括至少一个电容器，至少一个比较器和用于对至少一个电容器充电或放电的至少一个装置。 电容器耦合到比较器。 比较器将电容器上的电压与参考电压进行比较，并激活器件，以指示电容器的充电或放电。 振荡器还包括一个电路，用于当器件指令电容器的充电时，向比较器提供一个预置电压，以便比较器将预设电压减小的参考电压与电容器上的电压或电容器上的电压进行比较 用参考电压加到预设电压上。
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公开(公告)号：US20080301357A1
公开(公告)日：2008-12-04
申请号：US12113721
申请日：2008-05-01
申请人： Francesco La Rosa , Antonino Conte
发明人： Francesco La Rosa , Antonino Conte
IPC分类号： G06F12/02
CPC分类号： G11C16/225 , G11C16/102
摘要： A method writes data in a non-volatile memory. The method provides, in the memory, a non-volatile main memory area comprising target pages, a non-volatile auxiliary memory area comprising auxiliary pages, and, in the auxiliary memory area: a current sector comprising erased auxiliary pages usable to write data, a save sector comprising auxiliary pages comprising data linked to target pages to be erased or being erased, a transfer sector comprising auxiliary pages including data to be transferred to erased target pages, and an unavailable sector comprising auxiliary pages to be erased or being erased. The method can be applied in particular to FLASH memories.
摘要翻译： 一种方法将数据写入非易失性存储器。 该方法在存储器中提供包括目标页面的非易失性主存储器区域，包括辅助页面的非易失性辅助存储器区域，并且在辅助存储器区域中：包括可用于写入数据的已擦除辅助页面的当前扇区， 包括辅助页面的保存扇区，包括链接到要擦除或被擦除的目标页面的数据，包括辅助页面的传送扇区，包括要传送到已擦除的目标页面的数据，以及包括要被擦除或被擦除的辅助页面的不可用扇区。 该方法可以特别地应用于闪速存储器。
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60.发明授权Electrically word-erasable non-volatile memory device, and biasing method thereof 有权电可擦除非易失性存储器件及其偏置方法公开(公告)号：US07130219B2
公开(公告)日：2006-10-31
申请号：US11067478
申请日：2005-02-25
IPC分类号： G11C16/04
摘要： A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a plurality of P-type wells extending in a direction transverse to the rows. A plurality of main bitlines extend along the columns. Each P-type well is associated to a set of local bitlines that extend along the respective P-type well and are coupled to the drain terminals of the cells accommodated in the respective P-type well. Local-bitlines managing circuits are provided for each P-type well and are located between the main bitlines and a respective set of local bitlines for controllably connecting each local bitline to a respective main bitline.
摘要翻译： 由存储单元阵列形成的存储器件，其以行和列的形式延伸。 该装置由平行于行的多个N型阱形成; 每个N型井容纳沿横向于行的方向延伸的多个P型井。 多个主位线沿着列延伸。 每个P型阱与沿着相应P型阱延伸的一组本地位线相关联，并且耦合到容纳在相应P型阱中的单元的漏极端子。 为每个P型阱提供局部位线管理电路，并且位于主位线之间，并且位于相应的一组本地位线之间，用于可控地将每个本地位线连接到相应的主位线。
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