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1.发明授权Circuit for generating a reference voltage with compensation of the offset voltage 有权用于产生具有补偿偏移电压的参考电压的电路公开(公告)号：US08482342B2
公开(公告)日：2013-07-09
申请号：US12913682
申请日：2010-10-27
CPC分类号： G05F3/30 , H03F3/347 , H03F3/45183 , H03F2203/45466
摘要： An embodiment of a circuit includes first and second branches, an amplifier, a compensation circuit, and a bias unit. The first and second branches are respectively operable to generate first and second currents. The amplifier has a first amplifier input node coupled to the first branch, a second amplifier input node coupled to the second branch, an amplifier output node coupled to the first and second branches, and a first compensation node. The compensation unit is operable to provide a first offset-compensation signal to the first compensation node. And the first bias unit is operable to provide first and second bias signals to the first and second input nodes, respectively, such that the amplifier is operable to cause the first current to approximately equal the second current.
摘要翻译： 电路的一个实施例包括第一和第二分支，放大器，补偿电路和偏置单元。 第一和第二分支分别可操作以产生第一和第二电流。 放大器具有耦合到第一分支的第一放大器输入节点，耦合到第二分支的第二放大器输入节点，耦合到第一和第二分支的放大器输出节点和第一补偿节点。 补偿单元可操作以向第一补偿节点提供第一偏移补偿信号。 并且第一偏置单元可操作以分别向第一和第二输入节点提供第一和第二偏置信号，使得放大器可操作以使第一电流近似等于第二电流。
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公开(公告)号：US08704588B2
公开(公告)日：2014-04-22
申请号：US12913658
申请日：2010-10-27
CPC分类号： G05F3/30 , H03F3/347 , H03F3/45183 , H03F2203/45466
摘要： A bandgap voltage reference circuit for generating a bandgap voltage reference. An embodiment comprises a current generator controlled by a first driving voltage for generating a first current depending on the driving voltage, and a first reference circuit element coupled to the controlled current generator for receiving the first current and generating a first reference voltage in response to the first current. The circuit further comprises a second reference circuit element for receiving a second current corresponding to the first current; said second reference circuit element is adapted to generate a second reference voltage in response to the second current. The circuit further comprises an operational amplifier having a first input coupled to the first circuit element and a second input coupled to the second reference circuit element. The circuit also comprises a control circuit comprising first capacitive element and second capacitive element.
摘要翻译： 一种用于产生带隙电压基准的带隙电压参考电路。 一个实施例包括由第一驱动电压控制的电流发生器，用于根据驱动电压产生第一电流，以及耦合到受控电流发生器的第一参考电路元件，用于接收第一电流并响应于第一电压产生第一参考电压 第一流。 电路还包括用于接收对应于第一电流的第二电流的第二参考电路元件; 所述第二参考电路元件适于响应于第二电流产生第二参考电压。 电路还包括具有耦合到第一电路元件的第一输入和耦合到第二参考电路元件的第二输入的运算放大器。 该电路还包括一个包括第一电容元件和第二电容元件的控制电路。
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3.发明授权公开(公告)号：US07576591B2
公开(公告)日：2009-08-18
申请号：US11780206
申请日：2007-07-19
申请人： Antonino Conte , Carmelo Ucciardello , Carmine D'Alessandro , Mario Micciche , Giovanni Matranga , Diego De Costantini
发明人： Antonino Conte , Carmelo Ucciardello , Carmine D'Alessandro , Mario Micciche , Giovanni Matranga , Diego De Costantini
IPC分类号： G05F1/10
摘要： A charge pump system is provided that includes at least one first pump for generating a first working voltage, a second pump for generating a second working voltage, and a third pump for generating a third working voltage. The first pump is connected to an internal supply voltage reference that can having a limited value, and has an output terminal connected to the second and third pumps so as to supplying them with the first working voltage as their supply voltage. A method is also provided for managing the generation of voltages to be used with such a charge pump system.
摘要翻译： 提供一种电荷泵系统，其包括用于产生第一工作电压的至少一个第一泵，用于产生第二工作电压的第二泵和用于产生第三工作电压的第三泵。 第一泵连接到可以具有有限值的内部电源参考电压，并且具有连接到第二和第三泵的输出端，以便向它们提供第一工作电压作为它们的电源电压。 还提供了一种用于管理与这种电荷泵系统一起使用的电压的产生的方法。
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4.发明申请SENSE-AMPLIFIER CIRCUIT FOR NON-VOLATILE MEMORIES THAT OPERATES AT LOW SUPPLY VOLTAGES 有权用于低电压下运行的非易失性存储器的感应放大器电路公开(公告)号：US20110069554A1
公开(公告)日：2011-03-24
申请号：US12883072
申请日：2010-09-15
IPC分类号： G11C16/06
摘要： A sense-amplifier circuit includes: a comparison stage that compares a cell current that flows in a memory cell and through an associated bitline, with a reference current, for supplying an output signal indicating the state of the memory cell; and a precharging stage, which supplies, during a precharging step prior to the comparison step, a precharging current to the bitline so as to charge a capacitance thereof. The comparison stage includes a first comparison transistor and by a second comparison transistor, which are coupled in current-mirror configuration respectively to a first differential output and to a second differential output, through which a biasing current flows. The precharging stage diverts, during the precharging step, the biasing current towards the bitline as precharging current, and allows, during the comparison step, passage of part of the biasing current towards the first differential output, enabling operation of the current mirror.
摘要翻译： 感测放大器电路包括：比较级，其将存储单元中流动的单元电流和相关联的位线与参考电流进行比较，用于提供指示存储单元的状态的输出信号; 以及预充电阶段，其在比较步骤之前的预充电步骤期间向位线提供预充电电流以对其电容充电。 比较级包括第一比较晶体管和第二比较晶体管，其以电流镜配置分别耦合到第一差分输出和偏置电流流过的第二差分输出。 预充电阶段在预充电步骤期间将作为预充电电流的朝向位线的偏置电流转移，并且在比较步骤期间允许偏置电流的一部分朝向第一差分输出通过，使得能够操作电流镜。
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5.发明申请CIRCUIT AND METHOD FOR GENERATING A REFERENCE VOLTAGE IN MEMORY DEVICES HAVING A NON-VOLATILE CELL MATRIX 有权在具有非易失性单元矩阵的存储器件中产生参考电压的电路和方法公开(公告)号：US20080130361A1
公开(公告)日：2008-06-05
申请号：US11941688
申请日：2007-11-16
申请人： Antonino Conte , Mario Micciche , Gianbattista Lo Giudice , Alberto Di Martino , Giampiero Sberno
发明人： Antonino Conte , Mario Micciche , Gianbattista Lo Giudice , Alberto Di Martino , Giampiero Sberno
CPC分类号： G11C16/30
摘要： A generator circuit generates a reference voltage on an output terminal connected to a matrix of non-volatile memory cells and includes a comparator positioned between a common node and the output terminal. The comparator has first and second input terminals and an output terminal suitable for supplying a compared voltage given by comparing first and second voltage values present on the first and second input terminals. The circuit includes a reference cell inserted between the common node and a first voltage reference. Advantageously, the reference cell comprises a floating gate with a contact terminal coupled to a biasing block, having an input terminal connected to the output terminal of the generator circuit and being suitable for periodically biasing the floating gate contact terminal at a biasing voltage of a second voltage reference.
摘要翻译： 发电机电路在连接到非易失性存储器单元矩阵的输出端上产生参考电压，并且包括位于公共节点和输出端之间的比较器。 比较器具有第一和第二输入端子和适于提供通过比较第一和第二输入端子上存在的第一和第二电压值给出的比较电压的输出端子。 电路包括插入公共节点和第一电压基准之间的参考单元。 有利地，参考单元包括具有耦合到偏置块的接触端子的浮动栅极，其具有连接到发生器电路的输出端子的输入端子，并且适于在第二个偏置电压周期性地偏置浮置栅极接触端子 电压参考。
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6.发明授权Sense-amplifier circuit for non-volatile memories that operates at low supply voltages 有权用于在低电源电压下工作的非易失性存储器的感应放大器电路公开(公告)号：US08437196B2
公开(公告)日：2013-05-07
申请号：US12883072
申请日：2010-09-15
IPC分类号： G11C16/06
摘要： A sense-amplifier circuit includes: a comparison stage that compares a cell current that flows in a memory cell and through an associated bitline, with a reference current, for supplying an output signal indicating the state of the memory cell; and a precharging stage, which supplies, during a precharging step prior to the comparison step, a precharging current to the bitline so as to charge a capacitance thereof. The comparison stage includes a first comparison transistor and by a second comparison transistor, which are coupled in current-mirror configuration respectively to a first differential output and to a second differential output, through which a biasing current flows. The precharging stage diverts, during the precharging step, the biasing current towards the bitline as precharging current, and allows, during the comparison step, passage of part of the biasing current towards the first differential output, enabling operation of the current mirror.
摘要翻译： 感测放大器电路包括：比较级，其将存储单元中流动的单元电流和相关联的位线与参考电流进行比较，用于提供指示存储单元的状态的输出信号; 以及预充电阶段，其在比较步骤之前的预充电步骤期间向位线提供预充电电流以对其电容充电。 比较级包括第一比较晶体管和第二比较晶体管，其以电流镜配置分别耦合到第一差分输出和偏置电流流过的第二差分输出。 预充电阶段在预充电步骤期间将作为预充电电流的朝向位线的偏置电流转移，并且在比较步骤期间允许偏置电流的一部分朝向第一差分输出通过，使得能够操作电流镜。
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7.发明授权公开(公告)号：US08994355B2
公开(公告)日：2015-03-31
申请号：US13401078
申请日：2012-02-21
CPC分类号： H02M3/073
摘要： A voltage converter device includes a voltage regulator having a supply terminal for receiving a supply voltage and an output terminal for providing a regulated voltage. A voltage multiplier is for receiving the regulated voltage and providing a boosted voltage higher in absolute value than the regulated voltage. The voltage multiplier includes circuitry for providing a clock signal that switches periodically between the regulated voltage and a reference voltage, and a sequence of capacitive stages that alternately accumulate and transfer electric charge according to the clock signal for generating the boosted voltage from the regulated voltage. The voltage regulator includes a power transistor and a regulation transistor each having a first conduction terminal, a second conduction terminal and a control terminal.
摘要翻译： 电压转换器装置包括具有用于接收电源电压的电源端子和用于提供调节电压的输出端子的电压调节器。 电压倍增器用于接收调节电压并提供绝对值高于调节电压的升压电压。 电压倍增器包括用于提供在调节电压和参考电压之间周期性切换的时钟信号的电路，以及根据时钟信号交替地累积和传送电荷的电容级序列，用于从调节电压产生升压电压。 电压调节器包括功率晶体管和调节晶体管，每个具有第一导电端子，第二导电端子和控制端子。
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8.发明授权Circuit and method for generating a reference voltage in memory devices having a non-volatile cell matrix 有权用于在具有非易失性单元矩阵的存储器件中产生参考电压的电路和方法公开(公告)号：US07633805B2
公开(公告)日：2009-12-15
申请号：US11941688
申请日：2007-11-16
申请人： Antonino Conte , Mario Micciche , Gianbattista Lo Giudice , Alberto Di Martino , Giampiero Sberno
发明人： Antonino Conte , Mario Micciche , Gianbattista Lo Giudice , Alberto Di Martino , Giampiero Sberno
IPC分类号： G11C11/34
CPC分类号： G11C16/30
摘要： A generator circuit generates a reference voltage on an output terminal connected to a matrix of non-volatile memory cells and includes a comparator positioned between a common node and the output terminal. The comparator has first and second input terminals and an output terminal suitable for supplying a compared voltage given by comparing first and second voltage values present on the first and second input terminals. The circuit includes a reference cell inserted between the common node and a first voltage reference. Advantageously, the reference cell comprises a floating gate with a contact terminal coupled to a biasing block, having an input terminal connected to the output terminal of the generator circuit and being suitable for periodically biasing the floating gate contact terminal at a biasing voltage of a second voltage reference.
摘要翻译： 发电机电路在连接到非易失性存储器单元矩阵的输出端上产生参考电压，并且包括位于公共节点和输出端之间的比较器。 比较器具有第一和第二输入端子和适于提供通过比较第一和第二输入端子上存在的第一和第二电压值给出的比较电压的输出端子。 电路包括插入公共节点和第一电压基准之间的参考单元。 有利地，参考单元包括具有耦合到偏置块的接触端子的浮动栅极，其具有连接到发生器电路的输出端子的输入端子，并且适于在第二个偏置电压周期性地偏置浮置栅极接触端子 电压参考。
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9.发明申请METHOD FOR GENERATING A REFERENCE CURRENT AND A RELATED FEEDBACK GENERATOR 审中-公开用于产生参考电流的方法和相关的反馈发生器公开(公告)号：US20080001592A1
公开(公告)日：2008-01-03
申请号：US11763679
申请日：2007-06-15
IPC分类号： G05F3/20
CPC分类号： G05F1/46
摘要： A feedback generator of a reference current may include a differential amplifier having a first input for a reference voltage, and a second input for a feedback voltage and generating an output voltage. The feedback generator may also include a first conduction path including a feedback resistor with the feedback voltage applied thereon, and a first transistor controlled by the output voltage and forcing through the feedback resistor the reference current. The feedback generator may also include a second conduction path coupled to the differential amplifier and biasing the differential amplifier based upon the reference current.
摘要翻译： 参考电流的反馈发生器可以包括具有用于参考电压的第一输入和用于反馈电压的第二输入并产生输出电压的差分放大器。 反馈发生器还可以包括第一导电路径，其包括其上施加有反馈电压的反馈电阻器，以及由输出电压控制并通过反馈电阻器施加参考电流的第一晶体管。 反馈发生器还可以包括耦合到差分放大器的第二导电路径，并且基于参考电流偏置差分放大器。
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10.发明申请Electrically word-erasable non-volatile memory device, and biasing method thereof 有权电可擦除非易失性存储器件及其偏置方法公开(公告)号：US20050195654A1
公开(公告)日：2005-09-08
申请号：US11067478
申请日：2005-02-25
摘要： A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a plurality of P-type wells extending in a direction transverse to the rows. A plurality of main bitlines extend along the columns. Each P-type well is associated to a set of local bitlines that extend along the respective P-type well and are coupled to the drain terminals of the cells accommodated in the respective P-type well. Local-bitlines managing circuits are provided for each P-type well and are located between the main bitlines and a respective set of local bitlines for controllably connecting each local bitline to a respective main bitline.
摘要翻译： 由存储单元阵列形成的存储器件，其以行和列的形式延伸。 该装置由平行于行的多个N型阱形成; 每个N型井容纳沿横向于行的方向延伸的多个P型井。 多个主位线沿着列延伸。 每个P型阱与沿着相应P型阱延伸的一组本地位线相关联，并且耦合到容纳在相应P型阱中的单元的漏极端子。 为每个P型阱提供局部位线管理电路，并且位于主位线之间，并且位于相应的一组本地位线之间，用于可控地将每个本地位线连接到相应的主位线。
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