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    Compact SRAMs and other multiple transistor structures
    51.
    发明授权
    Compact SRAMs and other multiple transistor structures 有权
    紧凑型SRAM和其他多晶体管结构

    公开(公告)号：US07365398B2

    公开(公告)日：2008-04-29

    申请号：US11055014

    申请日：2005-02-11

    申请人： Sandip Tiwari ,  Arvind Kumar

    发明人： Sandip Tiwari ,  Arvind Kumar

    IPC分类号： H01L29/76 ,  G11C11/00

    CPC分类号： H01L27/1104 ,  H01L27/11

    摘要： A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.

    摘要翻译： 高密度形式的静态随机存取存储器（SRAM）利用了硅两面的晶体管栅极和通过绝缘体上硅和三维集成的复杂形式实现的高互连性。 这种技术允许通过利用两侧的门的放置，在3D中形成常见的接触和密集的互连，从而非常紧凑地形成p沟道和n沟道器件。

    Internet based network topology discovery
    52.
    发明申请
    Internet based network topology discovery 审中-公开
    基于互联网的网络拓扑发现

    公开(公告)号：US20070294409A1

    公开(公告)日：2007-12-20

    申请号：US11893868

    申请日：2007-08-17

    申请人： Arvind Kumar

    发明人： Arvind Kumar

    IPC分类号： G06F15/173 ,  G06F17/30

    CPC分类号： H04L41/12 ,  H04L41/0266

    摘要： A system and method are provided for internet-based network topology discovery. A server in communication with a client, the server having a console having a managing device is provided to manage one or more network devices. A search engine is provided that is in communication with the managing device via a network including the Internet, the search engine capable of being accessed via the client. The console is used to formulate an Extensible Markup Language (XML) discovery information query, wherein the XML discovery information query is initiated automatically by the client. The console is further to send the XML discovery information query to the search engine to facilitate searching of discovery information relevant to the one or more network devices, wherein at least one of the one or more network devices includes an XML discovery information file, wherein at least one of the one or more network devices does not include the XML discovery information file. In response to sending the XML discovery information query, the console to receive one or more of the following via the search engine: first discovery information from the one or more network devices having the XML discovery information file, and second discovery information from a proxy device for the one or more network devices not including the XML discovery information files. The console is further used to generate a network topology map for the one or more network devices via the retrieved first and second discovery information.

    摘要翻译： 提供了一种基于互联网的网络拓扑发现的系统和方法。 提供与客户端通信的服务器，具有控制台的服务器具有管理设备以管理一个或多个网络设备。 提供了一种搜索引擎，其经由包括因特网的网络与管理设备通信，该搜索引擎能够经由客户机访问。 控制台用于制定可扩展标记语言（XML）发现信息查询，其中XML发现信息查询由客户端自动启动。 所述控制台还将所述XML发现信息查询发送到所述搜索引擎，以便于搜索与所述一个或多个网络设备相关的发现信息，其中所述一个或多个网络设备中的至少一个包括XML发现信息文件，其中， 一个或多个网络设备中的至少一个不包括XML发现信息文件。 响应于发送XML发现信息查询，控制台通过搜索引擎接收以下一个或多个：具有XML发现信息文件的一个或多个网络设备的第一发现信息和来自代理设备的第二发现信息 对于不包括XML发现信息文件的一个或多个网络设备。 控制台还用于通过检索的第一和第二发现信息为一个或多个网络设备生成网络拓扑图。

    Substrate solution for back gate controlled SRAM with coexisting logic devices
    53.
    发明申请
    Substrate solution for back gate controlled SRAM with coexisting logic devices 有权
    用于具有共存逻辑器件的背栅控制SRAM的衬底解决方案

    公开(公告)号：US20070138533A1

    公开(公告)日：2007-06-21

    申请号：US11311462

    申请日：2005-12-19

    申请人： Robert Dennard ,  Wilfried Haensch ,  Arvind Kumar ,  Robert Miller

    发明人： Robert Dennard ,  Wilfried Haensch ,  Arvind Kumar ,  Robert Miller

    IPC分类号： H01L29/76

    CPC分类号： H01L27/1108

    摘要： A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device

    摘要翻译： 一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂 提供了特定的水平，以提高不同器件区域内的FET器件的性能。 特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。 为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。 在源极/漏极区域之下具有低净掺杂的无均匀横向掺杂分布以及在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制

    Compact SRAMs and other multiple transistor structures
    55.
    发明申请
    Compact SRAMs and other multiple transistor structures 有权
    紧凑型SRAM和其他多晶体管结构

    公开(公告)号：US20050224994A1

    公开(公告)日：2005-10-13

    申请号：US11055014

    申请日：2005-02-11

    申请人： Sandip Tiwari ,  Arvind Kumar

    发明人： Sandip Tiwari ,  Arvind Kumar

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L31/062

    CPC分类号： H01L27/1104 ,  H01L27/11

    摘要： A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.

    摘要翻译： 高密度形式的静态随机存取存储器（SRAM）利用了硅两面的晶体管栅极和通过绝缘体上硅和三维集成的复杂形式实现的高互连性。 这种技术允许通过利用两侧的门的放置，在3D中形成常见的接触和密集的互连，从而非常紧凑地形成p沟道和n沟道器件。

    Method for remotely accessing component management information
    58.
    发明授权
    Method for remotely accessing component management information 失效
    用于远程访问组件管理信息的方法

    公开(公告)号：US06665731B1

    公开(公告)日：2003-12-16

    申请号：US09572422

    申请日：2000-05-16

    申请人： Arvind Kumar ,  Christopher C. Pearson

    发明人： Arvind Kumar ,  Christopher C. Pearson

    IPC分类号： G06F1516

    CPC分类号： H04L41/0226 ,  H04L29/06 ,  H04L41/0253 ,  H04L41/0266 ,  H04L41/0273 ,  H04L67/025

    摘要： Remotely executing programs access hardware components and upload component management information from these hardware components bypassing the operating system otherwise controlling the hardware components. A web-based browser application executes on a personal computer that is coupled to the Internet and accesses the hardware component information. Another computer that is also connected to the Internet hosts the hardware components that the web-based browser application wishes to access. The operating system of the second computer controls the operation of the hardware components. An adapter routine executing on an intermediate server, to which the hardware components are coupled and are capable of transferring component information in a predetermined format, serves as an intermediary between the web-based browser application and the hardware components. The format that the data is being transferred from the hardware components to the adapter routine is not compatible with the web-based browser application. The adapter routine converts data from the hardware components to a format acceptable to the web-based browser application, such as, for example, XML over HTTP, or any other computer language acceptable to the web-based browser application. The adapter routine also converts commands from the web-based browser application to the predetermined format required by the hardware components, such as, for example, IPMI or DMI. The web-based browser application interacts with the hardware components in a way that was heretofore not possible.

    摘要翻译： 远程执行程序访问硬件组件，并通过绕过操作系统的硬件组件上传组件管理信息，否则控制硬件组件。 基于Web的浏览器应用程序在耦合到因特网并访问硬件组件信息的个人计算机上执行。 也连接到互联网的另一台计算机托管基于Web的浏览器应用程序希望访问的硬件组件。 第二台计算机的操作系统控制硬件组件的运行。 在中间服务器上执行的适配器例程，硬件组件耦合到中间服务器并且能够以预定格式传送组件信息，用作基于web的浏览器应用程序和硬件组件之间的中介。 数据从硬件组件传输到适配器例程的格式与基于Web的浏览器应用程序不兼容。 适配器例程将来自硬件组件的数据转换为基于Web的浏览器应用程序可接受的格式，例如，基于HTTP的XML或基于Web的浏览器应用程序可接受的任何其他计算机语言。 适配器例程还将来自基于web的浏览器应用程序的命令转换为硬件组件所需的预定格式，例如IPMI或DMI。 基于Web的浏览器应用程序以前所未有的方式与硬件组件进行交互。

    Floating back gate electrically erasable programmable read-only memory (EEPROM)
    59.
    发明授权
    Floating back gate electrically erasable programmable read-only memory (EEPROM) 失效
    浮动后门电可擦除可编程只读存储器（EEPROM）

    公开(公告)号：US06248626B1

    公开(公告)日：2001-06-19

    申请号：US09116987

    申请日：1998-07-17

    申请人： Arvind Kumar ,  Sandip Tiwari

    发明人： Arvind Kumar ,  Sandip Tiwari

    IPC分类号： H01L2176

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/1203 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885

    摘要： A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.

    摘要翻译： 一种半导体存储器和一种制造存储器的方法，包括：晶体管，包括具有氧化物的第一栅极和沟道，以及包括第二栅极和其上的氧化物的背面，与第二栅极 晶体管，第二栅极包括浮置栅极，其中背面的氧化物的厚度与晶体管的第一栅极的氧化物分开地可分级。