公开(公告)号：US06445032B1

公开(公告)日：2002-09-03

申请号：US09072293

申请日：1998-05-04

Applicant: Arvind Kumar ,  Sandip Tiwari

Inventor： Arvind Kumar ,  Sandip Tiwari

IPC: H01L29788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/1203 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885

Abstract: A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.

Abstract translation: 一种半导体存储器和一种制造存储器的方法，包括：晶体管，包括具有氧化物的第一栅极和沟道，以及包括第二栅极和其上的氧化物的背面，与第二栅极 晶体管，第二栅极包括浮置栅极，其中背面的氧化物的厚度与晶体管的第一栅极的氧化物分开地可分级。

公开(公告)号：US06534819B2

公开(公告)日：2003-03-18

申请号：US09943210

申请日：2001-08-30

Applicant: Sandip Tiwari ,  Arvind Kumar

Inventor： Sandip Tiwari ,  Arvind Kumar

IPC: H01L2976

CPC classification number: H01L21/76254 ,  G11C16/0441 ,  H01L27/115 ,  H01L27/1203 ,  Y10S257/903

Abstract: A two transistor programmable logic cell 100 is used in programmable logic devices. The cell 100 has a backgate 3 that holds charge to program one of the two transistors into a logic 1 or a logic 0 state. Programmable logic devices are scalable to fine geometries and high densities and may be programmed to perform multiple logic functions on the same substrate.

公开(公告)号：US07365398B2

公开(公告)日：2008-04-29

申请号：US11055014

申请日：2005-02-11

Applicant: Sandip Tiwari ,  Arvind Kumar

Inventor： Sandip Tiwari ,  Arvind Kumar

IPC: H01L29/76 ,  G11C11/00

CPC classification number: H01L27/1104 ,  H01L27/11

Abstract: A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.

Abstract translation: 高密度形式的静态随机存取存储器（SRAM）利用了硅两面的晶体管栅极和通过绝缘体上硅和三维集成的复杂形式实现的高互连性。 这种技术允许通过利用两侧的门的放置，在3D中形成常见的接触和密集的互连，从而非常紧凑地形成p沟道和n沟道器件。

公开(公告)号：US20050224994A1

公开(公告)日：2005-10-13

申请号：US11055014

申请日：2005-02-11

Applicant: Sandip Tiwari ,  Arvind Kumar

Inventor： Sandip Tiwari ,  Arvind Kumar

IPC: H01L21/8244 ,  H01L27/11 ,  H01L31/062

CPC classification number: H01L27/1104 ,  H01L27/11

Abstract: A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.

Abstract translation: 高密度形式的静态随机存取存储器（SRAM）利用了硅两面的晶体管栅极和通过绝缘体上硅和三维集成的复杂形式实现的高互连性。 这种技术允许通过利用两侧的门的放置，在3D中形成常见的接触和密集的互连，从而非常紧凑地形成p沟道和n沟道器件。

公开(公告)号：US06248626B1

公开(公告)日：2001-06-19

申请号：US09116987

申请日：1998-07-17

Applicant: Arvind Kumar ,  Sandip Tiwari

Inventor： Arvind Kumar ,  Sandip Tiwari

IPC: H01L2176

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/1203 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885

Abstract: A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.

Abstract translation: 一种半导体存储器和一种制造存储器的方法，包括：晶体管，包括具有氧化物的第一栅极和沟道，以及包括第二栅极和其上的氧化物的背面，与第二栅极 晶体管，第二栅极包括浮置栅极，其中背面的氧化物的厚度与晶体管的第一栅极的氧化物分开地可分级。

公开(公告)号：US20120280301A1

公开(公告)日：2012-11-08

申请号：US13322379

申请日：2010-05-28

Applicant: Sandip Tiwari ,  Ravishankar Sundararaman ,  Sang Hyeon Lee ,  Moonkyung Kim

Inventor： Sandip Tiwari ,  Ravishankar Sundararaman ,  Sang Hyeon Lee ,  Moonkyung Kim

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/685 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

Abstract: In one embodiment there is set forth a method comprising providing a semiconductor structure having an electrode, wherein the providing includes providing a phase transition material region and wherein the method further includes imparting energy to the phase transition material region to induce a phase transition of the phase transition material region. By inducing a phase transition of the phase transition material region, a state of the semiconductor structure can be changed. There is further set forth an apparatus comprising a structure including an electrode and a phase transition material region, wherein the apparatus is operative for imparting energy to the phase transition material region to induce a phase transition of the phase transition material region without the phase transition of the phase transition material region being dependent on electron transport through the phase transition material region.

Abstract translation: 在一个实施例中，提出了一种方法，包括提供具有电极的半导体结构，其中所述提供包括提供相变材料区域，并且其中所述方法还包括赋予相变材料区域能量以引起相位的相变 过渡材料区域。 通过引起相变材料区域的相变，可以改变半导体结构的状态。 还提出了一种装置，其包括包括电极和相变材料区域的结构，其中该装置可操作以将能量传递给相变材料区域，以引起相变材料区域的相变而不发生相变 相变材料区域依赖于通过相变材料区域的电子传输。

公开(公告)号：US20110049650A1

公开(公告)日：2011-03-03

申请号：US12549906

申请日：2009-08-28

Applicant: Sandip Tiwari ,  Moon-Kyung Kim ,  Joshua Mark Rubin ,  Soo-Doo Chae ,  Choong-Man Lee ,  Ravishankar Sundararaman

Inventor： Sandip Tiwari ,  Moon-Kyung Kim ,  Joshua Mark Rubin ,  Soo-Doo Chae ,  Choong-Man Lee ,  Ravishankar Sundararaman

IPC: H01L29/84

CPC classification number: H01L49/00 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00

Abstract: An electromechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode.

Abstract translation: 机电晶体管包括彼此间隔开的源电极和漏电极。 源极柱位于衬底和源电极之间。 漏极柱位于衬底和漏电极之间。 可移动通道与源电极和漏电极间隔开。 门纳米柱位于可移动通道和基板之间。 第一电介质层位于可移动沟道和栅极纳米柱之间。 第二电介质层位于源极柱和源极之间。 第三介电层位于漏极柱和漏极之间。

公开(公告)号：US06350321B1

公开(公告)日：2002-02-26

申请号：US09207353

申请日：1998-12-08

Applicant: Kevin K. Chan ,  Christopher P. D'Emic ,  Raymond M. Sicina ,  Paul M. Kozlowski ,  Margaret Manny ,  Sandip Tiwari

Inventor： Kevin K. Chan ,  Christopher P. D'Emic ,  Raymond M. Sicina ,  Paul M. Kozlowski ,  Margaret Manny ,  Sandip Tiwari

IPC: C23C1600

CPC classification number: H01L21/67225 ,  C23C14/56

Abstract: A cluster system controls the interface properties of the films that deposit or grow on a silicon substrate. The system comprises a plurality of horizontal quartz chamber or tubes each of which can hold a large quantity of wafers, a transfer chamber and a load/unload chamber. Several process steps can be executed sequentially in different tubes without intermediate exposure to ambient air. A transfer chamber connects them and allows wafer transportation from one tube to another in an absolute controlled UHV environment which limits any contamination such as H2O, to less than a monolayer level. In addition, each tube can be pumped down to UHV pressure regime to avoid further cross contamination between tubes or particle generation. Since some of the process requires elevated temperature, all wafers are placed vertically on the quartz boat to prevent any wafer sagging as in a vertical furnace. Furthermore, before any wafers are placed into the transfer chamber, they are loaded into a load/unload chamber, which is the sole connection to the ambient air, to be purged and pumped so as to minimize particles and contamination.

Abstract translation: 簇系统控制在硅衬底上沉积或生长的膜的界面性质。 该系统包括多个水平石英腔或管，每个水平的石英腔或管可以容纳大量的晶片，传送室和装载/卸载室。 可以在不同环境空气的情况下，在不同的管中顺序执行若干工艺步骤。 传输室连接它们，并允许晶片在绝对控制的特高压环境中从一个管到另一个管输送，将任何污染（例如H 2 O）限制到小于单层。 此外，每个管可以泵送到特高压压力状态，以避免管之间的进一步交叉污染或产生颗粒。 由于某些过程需要升高的温度，因此将所有晶片垂直放置在石英舟上，以防止垂直炉中出现任何晶片下垂。 此外，在将任何晶片放入转移室之前，它们被装载到与环境空气的唯一连接的装载/卸载室中，以被清除和泵送，以使颗粒和污染物最小化。

公开(公告)号：US4558509A

公开(公告)日：1985-12-17

申请号：US626563

申请日：1984-06-29

Applicant: Sandip Tiwari

Inventor： Sandip Tiwari

IPC: H01L21/225 ,  H01L21/324 ,  H01L21/338 ,  H01L29/04 ,  H01L29/812 ,  H01L21/265 ,  H01L21/20

CPC classification number: H01L29/045 ,  H01L21/2258 ,  H01L21/3245 ,  H01L29/812

Abstract: A method for forming a FET in a gallium arsenide substrate whereby a gate is positioned on a [100] surface of the gallium arsenide substrate in the [011] orientation, active impurities are ion implanted to form FET source and drain regions which are self-aligned with respect to the gate, and the structure is annealed subsequent to the ion implanting whereby the active impurities are caused to diffuse laterally and thereby form channel region beneath the gate.

Abstract translation: 一种用于在砷化镓衬底中形成FET的方法，其中栅极位于[011]取向的砷化镓衬底的[100]表面上，有源杂质被离子注入以形成FET源极和漏极区， 并且结构在离子注入之后被退火，由此使活性杂质横向扩散，从而形成栅极下方的沟道区域。

公开(公告)号：US09389511B2

公开(公告)日：2016-07-12

申请号：US14005964

申请日：2012-03-19

Applicant: Evan L. Schwartz ,  Wei Min Chan ,  Jin-Kyun Lee ,  Sandip Tiwari ,  Christopher K. Ober

Inventor： Evan L. Schwartz ,  Wei Min Chan ,  Jin-Kyun Lee ,  Sandip Tiwari ,  Christopher K. Ober

IPC: G03F7/26 ,  G03F7/16 ,  H01L21/027 ,  B81C1/00 ,  G03F7/038 ,  G03F7/00

CPC classification number: G03F7/16 ,  B81C1/00031 ,  B81C2201/0149 ,  G03F7/0002 ,  G03F7/038 ,  H01L21/027 ,  Y10T428/24851

Abstract: A method for forming patterns of organic polymer materials. The method can be used to form a layer with two patterned organic polymer materials. The photoresist and solvents used in the photoresist deposition and removal steps do not substantially affect the organic polymer materials.

Abstract translation: 一种形成有机聚合物材料图案的方法。 该方法可用于形成具有两个图案化有机聚合物材料的层。 在光致抗蚀剂沉积和去除步骤中使用的光致抗蚀剂和溶剂基本上不影响有机聚合物材料。