公开(公告)号：US10754582B2

公开(公告)日：2020-08-25

申请号：US16073534

申请日：2016-03-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Ali Shafiee Ardestani ,  Ben Feinberg

IPC: G06F13/00 ,  G06F3/06 ,  G06F12/02 ,  G11C13/00

Abstract: In an example, a method includes receiving input data and dividing the input data into a plurality of data portions, wherein the size of each data portion is based on a significance level. The input data may be assigned to at least one resistive memory array. Assigning the input data to at least one resistive memory array may comprises at least one of (i) assigning at least one data portion of the input data to be represented by a resistive memory array representing a number of bits, wherein the number of bits represented within the resistive memory array is based on the size of the at least one data portion; and (ii) processing each data portion of the input data with at least one resistive memory array.

公开(公告)号：US10585602B2

公开(公告)日：2020-03-10

申请号：US16011187

申请日：2018-06-18

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Doe Hyun Yoon ,  Naveen Muralimanohar ,  Jichuan Chang ,  Parthasarathy Ranganathan

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/10

Abstract: An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

公开(公告)号：US20190236111A1

公开(公告)日：2019-08-01

申请号：US16063793

申请日：2016-01-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Benjamin Feinberg ,  John Paul Strachan

IPC: G06F17/16 ,  G11C13/00

CPC classification number: G06F17/16 ,  G06G7/16 ,  G11C7/16 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069

Abstract: Example implementations of the present disclosure relate to in situ transposition of the data values in a memory array. An example system may include a non-volatile memory (NVM) array, including a plurality of NVM elements, usable in performance of computations. The example system may include an input engine to input a plurality of data values for storage by a corresponding plurality of original NVM elements. The example system may further include a transposition engine to direct performance of the in situ transposition such that the plurality of data values remains stored by the original NVM elements.

公开(公告)号：US10303622B2

公开(公告)日：2019-05-28

申请号：US15500460

申请日：2015-03-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Rajeev Balasubramonian ,  Naveen Muralimanohar ,  Gregg B. Lesartre ,  Paolo Faraboschi ,  Jishen Zhao

IPC: G06F21/00 ,  G06F12/14 ,  H03M7/30 ,  G06F3/06 ,  G06F11/10 ,  H03M13/09

Abstract: Techniques for writing data to a subset of memory devices are described. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise a set of memory devices. The block of data may be compressed. The compressed block of data may be written to a subset of the memory devices that comprise the line. The unwritten portions of the line may not be used to store valid data.

公开(公告)号：US20190042411A1

公开(公告)日：2019-02-07

申请号：US16073202

申请日：2016-03-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Ali Shafiee Ardestani

IPC: G06F12/0802 ,  G06F17/16 ,  G06N3/08

Abstract: In an example, a method includes identifying, using at least one processor, data portions of a plurality of distinct data objects stored in at least one memory which are to be processed using the same logical operation. The method may further include identifying a representation of an operand stored in at least one memory, the operand being to provide the logical operation and providing a logical engine with the operand. The data portions may be stored in a plurality of input data buffers, wherein each of the input data buffers comprises a data portion of a different data object. The logical operation may be carried out on each of the data portions using the logical engine, and the outputs for each data portion may be stored in a plurality of output data buffers, wherein each of the outputs comprising data derived from a different data object.

公开(公告)号：US20180373674A1

公开(公告)日：2018-12-27

申请号：US16052507

申请日：2018-08-01

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Miao Hu ,  John Paul Strachan ,  Naveen Muralimanohar

IPC: G06F17/14 ,  G06F17/15

Abstract: Examples herein relate to convolution accelerators. An example convolution accelerator may include a transformation crossbar array programmed to calculate a Fourier Transformation of a first vector with a transformation matrix and a Fourier Transformation of a second vector with the transformation matrix. A circuit of the example convolution accelerator may multiply the Fourier Transformation of the first vector with the Fourier Transformation of the second vector to calculate a product vector. The example convolution accelerator may have an inverse transformation crossbar array programmed to calculate an Inverse Fourier Transformation of the product vector according to an inverse transformation matrix.

公开(公告)号：US20180341623A1

公开(公告)日：2018-11-29

申请号：US16052516

申请日：2018-08-01

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Ali Shafiee Ardestani ,  Naveen Muralimanohar

IPC: G06F17/16 ,  G11C13/00 ,  G11C11/24 ,  G11C11/4096

Abstract: A circuit is provided. In an example, the circuit includes a memory array that includes a plurality of memory cells to store a matrix and a plurality of data lines coupled to the plurality of memory cells to provide a first set of values of the matrix. The circuit includes a multiplier coupled to the plurality of data lines to multiply the first set of values by a second set of values to produce a third set of values. A summing unit is included that is coupled to the multiplier to sum the third set of values to produce a sum. The circuit includes a shifting unit coupled to the summing unit to shift the sum and to add the shifted sum to a running total.

公开(公告)号：US10090030B1

公开(公告)日：2018-10-02

申请号：US15581159

申请日：2017-04-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ali Shafiee Ardestani ,  Naveen Muralimanohar ,  Brent Buchanan

IPC: G11C7/16 ,  G11C7/22 ,  H03M1/34 ,  H03K21/02 ,  H03M1/66

Abstract: Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.

公开(公告)号：US10055383B1

公开(公告)日：2018-08-21

申请号：US15581110

申请日：2017-04-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ali Shafiee Ardestani ,  Naveen Muralimanohar

IPC: G06F7/32 ,  G06F17/16 ,  G11C11/24 ,  G11C11/4096 ,  G11C13/00

CPC classification number: G06F17/16 ,  G11C7/1006 ,  G11C8/16 ,  G11C11/24 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79

Abstract: A circuit is provided. In an example, the circuit includes a memory array that includes a plurality of memory cells to store a matrix and a plurality of data lines coupled to the plurality of memory cells to provide a first set of values of the matrix. The circuit includes a multiplier coupled to the plurality of data lines to multiply the first set of values by a second set of values to produce a third set of values. A summing unit is included that is coupled to the multiplier to sum the third set of values to produce a sum. The circuit includes a shifting unit coupled to the summing unit to shift the sum and to add the shifted sum to a running total.

公开(公告)号：US20180113649A1

公开(公告)日：2018-04-26

申请号：US15571340

申请日：2016-03-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ali Shafiee Ardestani ,  Naveen Muralimanohar

IPC: G06F3/06 ,  G11C13/00

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/0688 ,  G06F13/16 ,  G06N3/063 ,  G11C7/1006 ,  G11C7/1039 ,  G11C13/0002 ,  G11C13/0023

Abstract: In an example, a method includes receiving, in a memory, input data to be processed in a first and a second processing layer. A processing operation of the second layer may be carried out on an output of a processing operation of the first processing layer. The method may further include assigning the input data to be processed according to at least one processing operation of the first layer, which may comprise using a resistive memory array, and buffering output data. It may be determined whether the buffered output data exceeds a threshold data amount to carry out at least one processing operation of the second layer and when it is determined that the buffered output data exceeds the threshold data amount, at least a portion of the buffered output data may be assigned to be processed according to a processing operation of the second layer.