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公开(公告)号：US10529394B2
公开(公告)日：2020-01-07
申请号：US16117509
申请日：2018-08-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Ali Shafiee Ardestani , Naveen Muralimanohar , Brent Buchanan
Abstract: Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.
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公开(公告)号：US20190065117A1
公开(公告)日：2019-02-28
申请号：US16073143
申请日：2016-03-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Ali Shafiee Ardestani
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0683 , G06F16/2237 , G06F16/2379 , G06J1/00 , G06T1/60 , G11C11/56 , G11C11/5685 , G11C13/0002
Abstract: In an example, a method comprises receiving a first matrix of values to be mapped to a resistive memory array, wherein each value in the matrix is to be represented as a resistance of a resistive memory element. An outlying value may be identified in the first matrix. At least one value of a portion of the first matrix containing the outlying value may be substituted with at least one substitute value to form a substituted first matrix.
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公开(公告)号：US11126549B2
公开(公告)日：2021-09-21
申请号：US16073202
申请日：2016-03-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Ali Shafiee Ardestani
Abstract: In an example, a method includes identifying, using at least one processor, data portions of a plurality of distinct data objects stored in at least one memory which are to be processed using the same logical operation. The method may further include identifying a representation of an operand stored in at least one memory, the operand being to provide the logical operation and providing a logical engine with the operand. The data portions may be stored in a plurality of input data buffers, wherein each of the input data buffers comprises a data portion of a different data object. The logical operation may be carried out on each of the data portions using the logical engine, and the outputs for each data portion may be stored in a plurality of output data buffers, wherein each of the outputs comprising data derived from a different data object.
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公开(公告)号：US10942673B2
公开(公告)日：2021-03-09
申请号：US15571340
申请日：2016-03-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ali Shafiee Ardestani , Naveen Muralimanohar
Abstract: In an example, a method includes receiving, in a memory, input data to be processed in a first and a second processing layer. A processing operation of the second layer may be carried out on an output of a processing operation of the first processing layer. The method may further include assigning the input data to be processed according to at least one processing operation of the first layer, which may comprise using a resistive memory array, and buffering output data. It may be determined whether the buffered output data exceeds a threshold data amount to carry out at least one processing operation of the second layer and when it is determined that the buffered output data exceeds the threshold data amount, at least a portion of the buffered output data may be assigned to be processed according to a processing operation of the second layer.
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公开(公告)号：US10754581B2
公开(公告)日：2020-08-25
申请号：US16073143
申请日：2016-03-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Ali Shafiee Ardestani
Abstract: In an example, a method comprises receiving a first matrix of values to be mapped to a resistive memory array, wherein each value in the matrix is to be represented as a resistance of a resistive memory element. An outlying value may be identified in the first matrix. At least one value of a portion of the first matrix containing the outlying value may be substituted with at least one substitute value to form a substituted first matrix.
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Patent Agency Ranking
公开(公告)号：US10664271B2
公开(公告)日：2020-05-26
申请号：US16073650
申请日：2016-01-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Ali Shafiee Ardestani
Abstract: Examples disclosed herein include a dot product engine, which includes a resistive memory array to receive an input vector, perform a dot product operation on the input vector and a stored vector stored in the memory array, and output an analog signal representing a result of the dot product operation. The dot product engine includes a stored negation indicator to indicate whether elements of the stored vector have been negated, and a digital circuit to generate a digital dot product result value based on the analog signal and the stored negation indicator.
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公开(公告)号：US20180374520A1
公开(公告)日：2018-12-27
申请号：US16117509
申请日：2018-08-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Ali Shafiee Ardestani , Naveen Muralimanohar , Brent Buchanan
CPC classification number: G11C7/22 , G11C7/16 , H03K21/02 , H03M1/1215 , H03M1/34 , H03M1/38 , H03M1/56 , H03M1/66
Abstract: Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.
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公开(公告)号：US10754582B2
公开(公告)日：2020-08-25
申请号：US16073534
申请日：2016-03-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Ali Shafiee Ardestani , Ben Feinberg
Abstract: In an example, a method includes receiving input data and dividing the input data into a plurality of data portions, wherein the size of each data portion is based on a significance level. The input data may be assigned to at least one resistive memory array. Assigning the input data to at least one resistive memory array may comprises at least one of (i) assigning at least one data portion of the input data to be represented by a resistive memory array representing a number of bits, wherein the number of bits represented within the resistive memory array is based on the size of the at least one data portion; and (ii) processing each data portion of the input data with at least one resistive memory array.
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公开(公告)号：US20190042411A1
公开(公告)日：2019-02-07
申请号：US16073202
申请日：2016-03-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Ali Shafiee Ardestani
IPC: G06F12/0802 , G06F17/16 , G06N3/08
Abstract: In an example, a method includes identifying, using at least one processor, data portions of a plurality of distinct data objects stored in at least one memory which are to be processed using the same logical operation. The method may further include identifying a representation of an operand stored in at least one memory, the operand being to provide the logical operation and providing a logical engine with the operand. The data portions may be stored in a plurality of input data buffers, wherein each of the input data buffers comprises a data portion of a different data object. The logical operation may be carried out on each of the data portions using the logical engine, and the outputs for each data portion may be stored in a plurality of output data buffers, wherein each of the outputs comprising data derived from a different data object.
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公开(公告)号：US20180341623A1
公开(公告)日：2018-11-29
申请号：US16052516
申请日：2018-08-01
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Ali Shafiee Ardestani , Naveen Muralimanohar
IPC: G06F17/16 , G11C13/00 , G11C11/24 , G11C11/4096
Abstract: A circuit is provided. In an example, the circuit includes a memory array that includes a plurality of memory cells to store a matrix and a plurality of data lines coupled to the plurality of memory cells to provide a first set of values of the matrix. The circuit includes a multiplier coupled to the plurality of data lines to multiply the first set of values by a second set of values to produce a third set of values. A summing unit is included that is coupled to the multiplier to sum the third set of values to produce a sum. The circuit includes a shifting unit coupled to the summing unit to shift the sum and to add the shifted sum to a running total.
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