公开(公告)号：US20180314927A1

公开(公告)日：2018-11-01

申请号：US15770430

申请日：2015-10-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  John Paul Strachan ,  Rajeev Balasubramonian ,  R. Stanley Williams

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/0635

Abstract: According to an example, a hybrid synaptic architecture based neural network may be implemented by determining, from input data, information that is to be recognized, mined, and/or synthesized by a plurality of analog neural cores. Further, the hybrid synaptic architecture based neural network may be implemented by determining, based on the information, selected ones of the plurality of analog neural cores that are to be actuated to identify a data subset of the input data to generate, based on the analysis of the data subset, results of the recognition, mining, and/or synthesizing of the information.

公开(公告)号：US20170220256A1

公开(公告)日：2017-08-03

申请号：US15500594

申请日：2015-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Rajeev Balasubramonian ,  Paolo Faraboschi ,  Gregg B. Lesartre ,  Naveen Muralimanohar

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0683 ,  G06F11/1048 ,  G06F11/1068 ,  G06F12/0238 ,  G06F12/1408 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/7208 ,  G11C29/52 ,  Y02D10/13

Abstract: Techniques for retrieving data blocks from memory devices are provided. In one aspect, a request to retrieve a block of data may be received. The block of data may be in a line in a rank of memory. The rank of memory may include multiple devices. The devices used to store the line in the rank of memory may be determined. The determined devices may be read.

公开(公告)号：US20160216912A1

公开(公告)日：2016-07-28

申请号：US15089730

申请日：2016-04-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Aniruddha Nagendran Udipi ,  Niladrish Chatterjee ,  Rajeev Balasubramonian ,  Alan Lynn Davis ,  Norman Paul Jouppi

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0658 ,  G06F3/0673 ,  G06F11/1088 ,  G06F12/0802 ,  G06F12/0893 ,  G06F2212/1028 ,  G06F2212/3042 ,  G06F2212/305 ,  G11C5/04 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4082 ,  Y02D10/13

Abstract: A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition the example apparatus includes a column decoder (606) to selectively activate a portion of the raw based on the column address and the signal asserted on the wordline.

Abstract translation: 所公开的示例性装置包括用于将对应于行（608）的行地址存储在存储器阵列（602）中的行地址寄存器（412）。 示例性装置还包括耦合到行地址寄存器的行解码器（604），用于在存储器接收列地址之后，在行的字线（704）上断言信号。 另外，示例性装置包括列解码器（606），用于基于列地址和在字线上断言的信号选择性地激活原始部分的一部分。

公开(公告)号：US10303622B2

公开(公告)日：2019-05-28

申请号：US15500460

申请日：2015-03-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Rajeev Balasubramonian ,  Naveen Muralimanohar ,  Gregg B. Lesartre ,  Paolo Faraboschi ,  Jishen Zhao

IPC: G06F21/00 ,  G06F12/14 ,  H03M7/30 ,  G06F3/06 ,  G06F11/10 ,  H03M13/09

Abstract: Techniques for writing data to a subset of memory devices are described. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise a set of memory devices. The block of data may be compressed. The compressed block of data may be written to a subset of the memory devices that comprise the line. The unwritten portions of the line may not be used to store valid data.

公开(公告)号：US20170315914A1

公开(公告)日：2017-11-02

申请号：US15522372

申请日：2014-10-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Rajeev Balasubramonian

IPC: G06F12/0806 ,  G06F12/0811 ,  G06F13/16

CPC classification number: G06F12/0806 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F13/161 ,  G06F13/1642 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/502 ,  G06F2212/621 ,  G11C7/00

Abstract: A method to access a memory chip having memory banks includes processing read requests in a read queue, and when a write queue is filled beyond a high watermark, stopping the processing of the read requests in the read queue and draining the write queue until the write queue is under a low watermark. Draining the write queue include issuing write requests in an order based on information in the read queue. When the write queue is under the low watermark, the method includes stopping the draining of the write queue and again processing the read requests in the read queue.

公开(公告)号：US20170271001A1

公开(公告)日：2017-09-21

申请号：US15500040

申请日：2015-01-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Rajeev Balasubramonian ,  Martin Foltin

IPC: G11C13/00

Abstract: A method of determining a current in a memory element of a crossbar array is described. In the method, a number of pre-access operations are initiated. Each pre-access operation includes discarding a previously stored sneak current, determining a new sneak current for the crossbar array, discarding a previously stored sneak current, and storing the new sneak current. In the method, in response to a received access command, an access voltage is applied to a target memory element of the crossbar array and an element current for the target memory element is determined based on an access current and a stored sneak current.

公开(公告)号：US10318420B2

公开(公告)日：2019-06-11

申请号：US15522372

申请日：2014-10-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Rajeev Balasubramonian

IPC: G11C7/00 ,  G06F13/16 ,  G06F12/084 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811

Abstract: A method to access a memory chip having memory banks includes processing read requests in a read queue, and when a write queue is filled beyond a high watermark, stopping the processing of the read requests in the read queue and draining the write queue until the write queue is under a low watermark. Draining the write queue include issuing write requests in an order based on information in the read queue. When the write queue is under the low watermark, the method includes stopping the draining of the write queue and again processing the read requests in the read queue.

公开(公告)号：US10254988B2

公开(公告)日：2019-04-09

申请号：US15500754

申请日：2015-03-12

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Rajeev Balasubramonian ,  Gregg B. Lesartre ,  Robert Schreiber ,  Jishen Zhao ,  Naveen Muralimanohar ,  Paolo Faraboschi

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G11C7/10 ,  G11C7/22 ,  G06F12/14

Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.

公开(公告)号：US09846550B2

公开(公告)日：2017-12-19

申请号：US15089730

申请日：2016-04-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Aniruddha Nagendran Udipi ,  Niladrish Chatterjee ,  Rajeev Balasubramonian ,  Alan Lynn Davis ,  Norman Paul Jouppi

IPC: G06F11/10 ,  G06F3/06 ,  G11C5/04 ,  G11C8/12 ,  G11C11/408 ,  G11C7/10 ,  G06F12/0893 ,  G06F12/0802

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0658 ,  G06F3/0673 ,  G06F11/1088 ,  G06F12/0802 ,  G06F12/0893 ,  G06F2212/1028 ,  G06F2212/3042 ,  G06F2212/305 ,  G11C5/04 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4082 ,  Y02D10/13

Abstract: A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.

公开(公告)号：US20170220488A1

公开(公告)日：2017-08-03

申请号：US15500460

申请日：2015-03-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Rajeev Balasubramonian ,  Naveen Muralimanohar ,  Gregg B. Lesartre ,  Paolo Faraboschi ,  Jishen Zhao

IPC: G06F12/14 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F12/1408 ,  G06F3/0619 ,  G06F3/0623 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/1012 ,  G06F11/1044 ,  G06F2212/1052 ,  G06F2212/402 ,  H03M7/30 ,  H03M7/6047 ,  H03M13/09

Abstract: Techniques for writing data to a subset of memory devices are described. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise a set of memory devices. The block of data may be compressed. The compressed block of data may be written to a subset of the memory devices that comprise the line. The unwritten portions of the line may not be used to store valid data.