公开(公告)号：US08772112B1

公开(公告)日：2014-07-08

申请号：US13830260

申请日：2013-03-14

Applicant: Hyundai Motor Company

Inventor： Dae Hwan Chun ,  Jong Seok Lee ,  Kyoung-Kook Hong ,  Youngkyun Jung

IPC: H01L21/336 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

Abstract: Disclosed is a method for fabricating a semiconductor device including: sequentially forming a first insulating film and a first barrier layer on a first surface of a substrate; etching the first barrier layer to form a first barrier layer pattern; etching the first insulating film to form a first insulating film pattern; removing the first barrier layer pattern and forming a first type epitaxial layer on an exposed first portion of the substrate; forming a second insulating film and a second barrier layer on the first type epitaxial layer and the first insulating film pattern; etching the second barrier layer to form a second barrier layer pattern; etching the second insulating film to form a second insulating film pattern, and etching the first insulating film pattern; and forming a second type epitaxial layer on an exposed second portion of the first surface of the n substrate.

Abstract translation: 公开了一种制造半导体器件的方法，包括：在衬底的第一表面上依次形成第一绝缘膜和第一阻挡层; 蚀刻第一阻挡层以形成第一阻挡层图案; 蚀刻第一绝缘膜以形成第一绝缘膜图案; 去除所述第一阻挡层图案并在所述基板的暴露的第一部分上形成第一类型的外延层; 在所述第一型外延层和所述第一绝缘膜图案上形成第二绝缘膜和第二阻挡层; 蚀刻所述第二阻挡层以形成第二阻挡层图案; 蚀刻第二绝缘膜以形成第二绝缘膜图案，并蚀刻第一绝缘膜图案; 以及在所述n基板的所述第一表面的暴露的第二部分上形成第二类型的外延层。

公开(公告)号：US20250022950A1

公开(公告)日：2025-01-16

申请号：US18524202

申请日：2023-11-30

Applicant: Hyundai Motor Company ,  Kia Corporation

Inventor： Junghee Park ,  Dae Hwan Chun ,  Jungyeop Hong ,  Youngkyun Jung ,  NackYong Joo

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/40 ,  H01L29/66

Abstract: An embodiment semiconductor device includes a conductive region extending in a first direction and a second direction intersecting the first direction and stacked in a third direction intersecting the first direction and the second direction and a termination region at an end of the conductive region in the first direction, wherein the termination region includes an n+ type substrate, an n− type layer disposed on an upper surface of the n+ type substrate and having a plurality of first trenches opening upward in the third direction, and a lower gate runner covering the plurality of first trenches and disposed on an upper surface of the n− type layer.

公开(公告)号：US20250022917A1

公开(公告)日：2025-01-16

申请号：US18524544

申请日：2023-11-30

Applicant: Hyundai Motor Company ,  Kia Corporation

Inventor： NackYong Joo ,  Dae Hwan Chun ,  Jungyeop Hong ,  Taehyun Kim ,  Youngkyun Jung ,  Junghee Park

IPC: H01L29/08 ,  H01L21/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: An embodiment semiconductor device includes an N− type layer having a trench therein, a P type region within the N− type layer, an N+ type region within the P type region, a gate electrode within the trench including a first gate electrode having an upper surface lower than an upper surface of the P type region and a second gate electrode having an upper surface lower than the upper surface of the first gate electrode, and source and drain electrodes insulated from the gate electrode, wherein the N+ type region includes a first N+ type region on a side of the first gate electrode and having a lower surface lower than the upper surface of the first gate electrode and a second N+ type region on a side of the second gate electrode and having a lower surface lower than the lower surface of the first N+ type region.

公开(公告)号：US20230246095A1

公开(公告)日：2023-08-03

申请号：US17835367

申请日：2022-06-08

Applicant: HYUNDAI MOTOR COMPANY ,  KIA CORPORATION

Inventor： NackYong Joo ,  Dae Hwan Chun ,  Jungyeop Hong ,  Youngkyun Jung ,  Junghee Park

IPC: H01L29/739 ,  H01L29/417 ,  H01L29/10 ,  H02M1/088 ,  H02M7/537

CPC classification number: H01L29/7397 ,  H01L29/41708 ,  H01L29/1095 ,  H02M1/088 ,  H02M7/537

Abstract: Provided is a semiconductor device including a semiconductor substrate, a plurality of gate electrodes disposed on the upper surface portion of the semiconductor substrate and spaced apart from each other, a plurality of emitter electrodes disposed to be overlapped with each of the plurality of gate electrodes, and a collector electrode disposed on the lower surface of the semiconductor substrate.

公开(公告)号：US20230020811A1

公开(公告)日：2023-01-19

申请号：US17569040

申请日：2022-01-05

Applicant: HYUNDAI MOTOR COMPANY ,  KIA CORPORATION

Inventor： Jungyeop Hong ,  Dae Hwan Chun ,  NackYong Joo ,  Youngkyun Jung ,  Junghee Park

IPC: H01L27/06 ,  H01L29/24 ,  H01L21/8258

Abstract: Disclosed is a semiconductor module including a substrate, a first semiconductor layer positioned on the substrate, an insulator positioned in a partial region on the first semiconductor layer, a second semiconductor layer positioned on the insulator, a first semiconductor device formed on the first semiconductor layer, and a second semiconductor device formed on the second semiconductor layer, wherein one of the first semiconductor layer and the second semiconductor layer includes gallium oxide (Ga2O3) and the other includes silicon (Si).

公开(公告)号：US20230016808A1

公开(公告)日：2023-01-19

申请号：US17544193

申请日：2021-12-07

Applicant: Hyundai Motor Company ,  Kia Corporation

Inventor： Dae Hwan Chun ,  Junghee Park ,  Jungyeop Hong ,  Youngkyun Jung ,  NackYong Joo

IPC: H01L29/267 ,  H01L21/02 ,  H01L29/06

Abstract: An embodiment semiconductor module includes a substrate, a heterogeneous thin film including a first semiconductor layer disposed on a first region of the substrate and a second semiconductor layer disposed on a second region of the substrate, a first semiconductor device disposed on the first semiconductor layer of the heterogeneous thin film, and a second semiconductor device disposed on the second semiconductor layer of the heterogeneous thin film, wherein one of the first semiconductor layer or the second semiconductor layer comprises gallium oxide (Ga2O3) and the other includes silicon (Si).

公开(公告)号：US20220208979A1

公开(公告)日：2022-06-30

申请号：US17514947

申请日：2021-10-29

Applicant: Hyundai Motor Company ,  Kia Corporation

Inventor： Junghee Park ,  Dae Hwan Chun ,  Jungyeop Hong ,  Youngkyun Jung ,  NackYong Joo

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/40

Abstract: A semiconductor device includes an n− type layer on a first surface of the substrate, a p type region on a part of the n− type layer, a gate on the n− type layer and the p type region, a first gate protection layer on the gate and a second gate protection layer on the first gate protection layer, a source on the second gate protection layer and the p type region, and a drain on the second surface of the substrate.

公开(公告)号：US10586877B2

公开(公告)日：2020-03-10

申请号：US16165414

申请日：2018-10-19

Applicant: Hyundai Motor Company ,  Kia Motors Corporation

Inventor： Dae Hwan Chun ,  NackYong Joo

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/417 ,  H01L29/16 ,  H01L21/02 ,  H01L21/04 ,  H01L29/66 ,  H01L29/36

Abstract: A semiconductor device may include: an n type of layer disposed on a first surface of a substrate; a p+ type of region disposed on the first surface of the substrate; a p− type of region disposed at a top portion of the n type of layer; a first electrode disposed on the p+ type of region and the p− type of region; and a second electrode disposed on a second surface of the substrate, wherein the side surface of the p+ type of region and the side surface of the n type of layer are in contact, and the thickness of the p+ type of region is the same as the thickness of the n type of layer and the thickness of the p− type of region.

公开(公告)号：US10396195B2

公开(公告)日：2019-08-27

申请号：US15980064

申请日：2018-05-15

Applicant: Hyundai Motor Company ,  Kia Motors Corporation

Inventor： Dae Hwan Chun

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/66

Abstract: A semiconductor device is provided and includes an n− type layer disposed at a substrate first surface. A trench, n type region, and p+ type region are disposed on the n− type layer. A p type region is disposed on the n type region. An n+ type region is disposed on the p type region. A gate insulating layer is disposed in the trench. A gate electrode is disposed on the gate insulating layer. A source electrode is disposed on an insulating layer disposed on the gate electrode, n+ type region, and p+ type region. A drain electrode is disposed at a substrate second surface. The n type region includes a first portion contacting the trench side surface and extending parallel to a substrate upper surface and a second portion contacting the first portion, separated from the trench side surface, and extending vertical to the substrate upper surface.

公开(公告)号：US10319851B2

公开(公告)日：2019-06-11

申请号：US15377708

申请日：2016-12-13

Applicant: Hyundai Motor Company

Inventor： Dae Hwan Chun ,  Youngkyun Jung ,  NackYong Joo ,  Junghee Park ,  JongSeok Lee

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/306 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L21/033

Abstract: A semiconductor device includes an n+ type silicon carbide substrate, an n− type layer, an n type layer, a plurality of trenches, a p type region, an n+ type region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and a channel. The plurality of trenches is disposed in a planar matrix shape. The n+ type region is disposed in a planar mesh type with openings, surrounds each of the trenches, and is in contact with the source electrode between the trenches adjacent to each other in a planar diagonal direction. The p type region is disposed in the opening of the n+ type region in a planar mesh type.