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51.发明授权Automated sensitivity definition and calibration for design for manufacturing tools 有权自动灵敏度定义和校准用于制造工具的设计公开(公告)号：US08141027B2
公开(公告)日：2012-03-20
申请号：US12652409
申请日：2010-01-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of automatic calibration of a design for manufacturing (DfM) simulation tool includes providing, as a first input, one or more defined rules for each of one or more semiconductor device levels to be simulated by the tool, and providing, as a second input, a plurality of defined feature size threshold ranges and increments for use in histogram generation of a number of failures with respect to a reference circuit; providing, as a third input, the reference circuit; executing the defined rules for the semiconductor device levels to be simulated, and outputting a fail count for the reference circuit at each defined threshold value, thereby generating histogram data of fail count versus threshold for the reference circuit; and providing, as a fourth input, a defined fail count metric, thereby calibrating the DfM tool for use with respect to a target circuit.
摘要翻译： 一种用于制造设计（DfM）模拟工具的自动校准的方法包括为由工具模拟的一个或多个半导体器件级别中的每一个提供一个或多个限定规则作为第一输入，并且作为第二输入提供第二 输入，多个定义的特征尺寸阈值范围和增量，用于相对于参考电路的多个故障的直方图生成; 提供参考电路作为第三输入; 执行要被模拟的半导体器件电平的限定规则，并在每个定义的阈值处输出参考电路的故障计数，由此产生参考电路的故障计数与阈值的直方图数据; 并且作为第四输入提供定义的故障计数度量，从而校准用于目标电路的DfM工具。
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52.发明授权Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool 有权使用关键区域分析工具计算VLSI设计对随机和系统缺陷的敏感度的方法公开(公告)号：US08132129B2
公开(公告)日：2012-03-06
申请号：US12348070
申请日：2009-01-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process.
摘要翻译： 估计集成电路产量的方法包括基于制造过程提供集成电路布局和一组系统缺陷。 接下来，该方法通过修改集成电路布局中的结构以产生修改的结构来表示系统缺陷。 更具体地，对于短路导致的缺陷，当结构包括较高的系统缺陷灵敏度水平时，该方法预先扩展结构，并且当结构包括较低的系统缺陷灵敏度水平时预结构。 接下来，使用改进的结构对集成电路布局进行关键区域分析，其中使用点投掷，几何展开或Voronoi图。 然后，该方法计算故障密度值，计算随机缺陷和系统缺陷。 随后将故障密度值与预定值进行比较，其中使用来自目标制造过程的测试结构和/或屈服数据确定预定值。
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53.发明申请公开(公告)号：US20110077916A1
公开(公告)日：2011-03-31
申请号：US12570195
申请日：2009-09-30
申请人： John M Cohn , Ulrich A. Finkler , David J. Hathaway , Jefrey G. Hemmett , Fook-Luen Heng , Jason D. Hibbeler , Gie Lee , Wayne H. Woods, JR. , Cole E. Zemke
发明人： John M Cohn , Ulrich A. Finkler , David J. Hathaway , Jefrey G. Hemmett , Fook-Luen Heng , Jason D. Hibbeler , Gie Lee , Wayne H. Woods, JR. , Cole E. Zemke
CPC分类号： G06F17/175
摘要： Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations.
摘要翻译： 用空间不均匀的统计学相关性与距离，标准偏差和通过统计学校正的空间插值的平均值来建模随机变量的方法。 该方法包括将统计独立的随机变量分配给坐标系中的一组种子点并在坐标系中的相应空间位置定义多个测试点。 通过从分配给种子点的一个或多个随机变量的空间插值，为每个测试点确定随机变量的等式。 该方法还包括利用相应的校正因子方程来调整每个测试点处的随机变量的方程。
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公开(公告)号：US20110025892A1
公开(公告)日：2011-02-03
申请号：US12534427
申请日：2009-08-03
IPC分类号： H04N5/335 , H01L31/112 , G06F17/50
CPC分类号： H01L27/14609 , H01L27/14641 , H01L27/14643 , H04N5/37457
摘要： A pixel structure for an image sensor includes a semiconductor material portion having a coplanar and contiguous semiconductor surface and including four photodiodes, four channel regions, and a common floating diffusion region. Each of the four channel regions is directly adjoined to one of the four photodiodes and the common floating diffusion region. The four photodiodes are located within four different quadrants as defined employing a vertical line passing through a point within the common floating diffusion region as a center axis. The common floating diffusion region, a reset gate transistor, a source follower transistor, and a row select transistor are located within four different quadrants as defined employing a vertical line passing through a point within one of the photodiodes as an axis.
摘要翻译： 图像传感器的像素结构包括具有共面且相邻的半导体表面的半导体材料部分，包括四个光电二极管，四个沟道区域和公共的浮动扩散区域。 四个通道区域中的每一个直接邻接四个光电二极管和公共浮动扩散区域中的一个。 四个光电二极管位于四个不同的象限内，如使用通过公共浮动扩散区域内的点作为中心轴的垂直线所限定的。 公共浮动扩散区域，复位栅极晶体管，源极跟随器晶体管和行选择晶体管位于四个不同的象限内，如使用通过一个光电二极管内的点作为轴的垂直线所限定的。
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55.发明授权Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique 有权基于使用开放确定性测序技术选择的样本窗口来分析集成电路的方法和系统公开(公告)号：US07752580B2
公开(公告)日：2010-07-06
申请号：US11828728
申请日：2007-07-26
申请人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
发明人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.
摘要翻译： 这里公开的是用于分析集成电路以确定该集成电路中的特定属性（即，物理或电气特性）的值的系统和相关方法的实施例。 在实施例中，使用开放确定性测序技术来选择表示集成电路布局中的样本窗口中心的点序列。 然后，为每个采样窗口确定特定属性的值，并累积结果，以推断整个集成电路布局的该特定属性的总体值。 这种测序技术具有允许添加附加样品窗口和/或改变窗口的尺寸和形状而不妨碍样品质量的优点。
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56.发明申请公开(公告)号：US20090113364A1
公开(公告)日：2009-04-30
申请号：US12325774
申请日：2008-12-01
申请人： Jeanne Paulette Spence Bickford , Jason D. Hibbeler , Juergen Koehl , William John Livingstone , Daniel Nelson Maynard
发明人： Jeanne Paulette Spence Bickford , Jason D. Hibbeler , Juergen Koehl , William John Livingstone , Daniel Nelson Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.
摘要翻译： 一种方法，装置，系统和计算机程序产品，其使用具有冗余和非冗余元件的集成电路上的关键区域分析来执行产量估计。 非冗余元素将被忽略或从对不需要的打开执行的关键区域分析中移除。
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57.发明申请METHOD FOR COMPUTING THE SENSISTIVITY OF A VLSI DESIGN TO BOTH RANDOM AND SYSTEMATIC DEFECTS USING A CRITICAL AREA ANALYSIS TOOL 有权使用关键领域分析工具计算VLSI设计对两个随机和系统缺陷的敏感度的方法公开(公告)号：US20090113360A1
公开(公告)日：2009-04-30
申请号：US12348070
申请日：2009-01-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process.
摘要翻译： 估计集成电路产量的方法包括基于制造过程提供集成电路布局和一组系统缺陷。 接下来，该方法通过修改集成电路布局中的结构以产生修改的结构来表示系统缺陷。 更具体地，对于短路导致的缺陷，当结构包括较高的系统缺陷灵敏度水平时，该方法预扩展结构，并且当结构包括较低的系统缺陷灵敏度水平时，预结构化。 接下来，使用改进的结构对集成电路布局进行关键区域分析，其中使用点投掷，几何展开或Voronoi图。 然后，该方法计算故障密度值，计算随机缺陷和系统缺陷。 随后将故障密度值与预定值进行比较，其中使用来自目标制造过程的测试结构和/或屈服数据确定预定值。
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公开(公告)号：US07496874B2
公开(公告)日：2009-02-24
申请号：US11275275
申请日：2005-12-21
申请人： Jeanne Paulette Spence Bickford , Jason D. Hibbeler , Juergen Koehl , William John Livingstone , Daniel Nelson Mayuard
发明人： Jeanne Paulette Spence Bickford , Jason D. Hibbeler , Juergen Koehl , William John Livingstone , Daniel Nelson Mayuard
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.
摘要翻译： 一种方法，装置和计算机程序产品，其使用具有冗余和非冗余元件的集成电路上的关键区域分析来执行产量估计。 非冗余元素将被忽略或从对不需要的打开执行的关键区域分析中移除。
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59.发明授权Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic 有权通过基于子网定时信息的冗余，通过经由网络/子网特征的源和/或目标的远距离路径来目标公开(公告)号：US07290226B2
公开(公告)日：2007-10-30
申请号：US10907496
申请日：2005-04-04
CPC分类号： G06F17/5068
摘要： Methods, systems and program products are disclosed that prioritize each target via for via redundancy based on at least one of the following: subnet timing information, a distance of a target via along a path from a driving source and a target via net/subnet characteristic, and attempt to add a redundant via to each target via based on the prioritization. The invention improves overall yield and reduces timing sensitivity to AC-related defects.
摘要翻译： 公开了方法，系统和程序产品，其基于以下至少一个来为每个目标优先化经过冗余：子网定时信息，目标通路沿着来自驱动源的路径和目标经由网络/子网特性的距离 ，并尝试根据优先级将冗余通道添加到每个目标。 本发明提高了整体产量并降低了与AC相关缺陷的时序灵敏度。
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60.发明授权公开(公告)号：US08234594B2
公开(公告)日：2012-07-31
申请号：US11552225
申请日：2006-10-24
申请人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
发明人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located at a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is approximately axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is approximately axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.
摘要翻译： 一种集成电路，包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线和位于距离第二线的第一距离的第四线 在第二级线路上。 第一通孔在第二导线的第一位置连接第一和第二导线。 第二通孔在第一位置处连接第二和第三导线，第二通孔大致轴向对准第一通孔。 第三通过在第四线的第二位置连接第三和第四导线。 在第二位置连接第一和第四导线的第四通孔，第四通孔与第三通孔大致轴向对齐。 第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。
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