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公开(公告)号：US20090057654A1
公开(公告)日：2009-03-05
申请号：US12197710
申请日：2008-08-25
CPC分类号： H01L29/66984 , B82Y25/00 , H01F10/3268 , H01L43/08
摘要： A spin FET of an aspect of the present invention includes source/drain regions, a channel region between the source/drain regions, and a gate electrode above the channel region. Each of the source/drain regions includes a stack structure which is comprised of a low work function material and a ferromagnet. The low work function material is a non-oxide which is comprised of one of Mg, K, Ca and Sc, or an alloy which includes the non-oxide of 50 at % or more.
摘要翻译： 本发明的一个自旋FET包括源极/漏极区域，源极/漏极区域之间的沟道区域和沟道区域上方的栅极电极。 源极/漏极区域中的每一个包括由低功函数材料和铁磁体组成的堆叠结构。 低功函数材料是由Mg，K，Ca和Sc中的一种或包含50原子％以上的非氧化物的合金构成的非氧化物。
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公开(公告)号：US20070164336A1
公开(公告)日：2007-07-19
申请号：US11610100
申请日：2006-12-13
CPC分类号： H01L29/66984 , G11C11/16 , H01L27/228 , H01L43/08 , H01L43/10
摘要： A spin FET according to an example of the present invention includes a magnetic pinned layer whose magnetization direction is fixed, a magnetic free layer whose magnetization direction is changed, a channel between the magnetic pinned layer and the magnetic free layer, a gate electrode provided on the channel via a gate insulation layer, and a multiferroric layer which is provided on the magnetic free layer, and whose magnetization direction is changed by an electric field.
摘要翻译： 根据本发明的示例的自旋FET包括其磁化方向固定的磁性钉扎层，其磁化方向改变的磁性自由层，磁性被钉扎层和磁性自由层之间的通道，设置在 通过栅极绝缘层的沟道，以及设置在磁性自由层上的磁化方向由电场改变的多层。
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公开(公告)号：US20060227465A1
公开(公告)日：2006-10-12
申请号：US11228326
申请日：2005-09-19
CPC分类号： H01F10/3231 , B82Y25/00 , G11C11/161 , G11C11/1675 , H01F10/3254 , H01F10/3272 , H01F10/3281 , H01L43/08 , H01L43/10
摘要： It is possible to reduce a current required for spin injection writing. A magneto-resistance effect element includes: a first magnetization pinned layer; a magnetization free layer; a tunnel barrier layer; a second magnetization pinned layer whose direction of magnetization is pinned to be substantially anti-parallel to the direction of magnetization of the first magnetization pinned layer, and; a non-magnetic layer. When the second magnetization pinned layer is made of ferromagnetic material including Co, material for the non-magnetic layer is metal including at least one element selected from the group consisting of Zr, Hf, Rh, Ag, and Au; when the second magnetization pinned layer is made of ferromagnetic material including Fe, material for the non-magnetic layer is metal including at least one element selected from the group consisting of Rh, Pt, Ir, Al, Ag, and Au; and when the second magnetization pinned layer is made of ferromagnetic material including Ni, material for the non-magnetic layer is metal including at least one element selected from the group consisting of Zr, Hf, Au, and Ag.
摘要翻译： 可以减少自旋注入写入所需的电流。 磁阻效应元件包括：第一磁化固定层; 无磁化层; 隧道势垒层; 第二磁化固定层，其磁化方向固定为与第一磁化固定层的磁化方向基本上反平行; 非磁性层。 当第二磁化固定层由包括Co的铁磁材料制成时，非磁性层的材料是包括选自Zr，Hf，Rh，Ag和Au中的至少一种元素的金属; 当第二磁化被钉扎层由包括Fe的铁磁材料制成时，用于非磁性层的材料是包括选自Rh，Pt，Ir，Al，Ag和Au中的至少一种元素的金属; 并且当第二磁化被钉扎层由包括Ni的铁磁材料制成时，用于非磁性层的材料是包括选自Zr，Hf，Au和Ag中的至少一种元素的金属。
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公开(公告)号：US08618590B2
公开(公告)日：2013-12-31
申请号：US12561475
申请日：2009-09-17
CPC分类号： H01L29/66984 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： A spin transistor includes a first ferromagnetic layer, a second ferromagnetic layer, a semiconductor layer between the first and second ferromagnetic layers, and a gate electrode on or above a surface of the semiconductor layer, the surface being between the first and second ferromagnetic layers. The first ferromagnetic layer comprises a ferromagnet which has a first minority spin band located at a high energy side and a second minority spin band located at a low energy side, and has a Fermi level in an area of the high energy side higher than a middle of a gap between the first and second minority spin bands.
摘要翻译： 自旋晶体管包括第一铁磁层，第二铁磁层，第一和第二铁磁层之间的半导体层，以及在半导体层的表面上或上方的栅电极，该表面位于第一和第二铁磁层之间。 第一铁磁层包括具有位于高能侧的第一少数自旋带和位于低能侧的第二少数自旋带的铁磁体，并且在高能量侧的区域中的费米能级高于中间 第一和第二少数自旋带之间的间隙。
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55.发明授权Spin MOSFET and reconfigurable logic circuit using the spin MOSFET 有权使用自旋MOSFET的Spin MOSFET和可重构逻辑电路公开(公告)号：US08487359B2
公开(公告)日：2013-07-16
申请号：US12486999
申请日：2009-06-18
IPC分类号： H01L27/108
CPC分类号： H01L29/66984 , B82Y25/00 , H01F10/3272 , H01F10/3286
摘要： It is made possible to provide a spin MOSFET that can minimize the increase in production costs and can perform both spin injection writing and reading. A spin MOSFET includes: a substrate that has a semiconductor region of a first conductivity type; first and second ferromagnetic stacked films that are formed at a distance from each other on the semiconductor region, and each have the same stacked structure comprising a first ferromagnetic layer, a nonmagnetic layer, and a second ferromagnetic layer stacked in this order, the second ferromagnetic stacked film having a film-plane area different from that of the first ferromagnetic stacked film; a gate insulating film that is formed on a portion of the semiconductor region, the portion being located between the first ferromagnetic stacked film and the second ferromagnetic stacked film; and a gate that is formed on the gate insulating film.
摘要翻译： 可以提供一种可以使生产成本增加最小化的自旋MOSFET，并且可以执行自动注入写入和读取两种操作。 自旋MOSFET包括：具有第一导电类型的半导体区域的衬底; 第一和第二铁磁层叠膜，其形成在半导体区域上彼此间隔一定距离处，并且各自具有包括依次层叠的第一铁磁层，非磁性层和第二铁磁层的相同层叠结构，第二铁磁体 具有与第一铁磁性层叠膜不同的膜面积的层叠膜; 形成在所述半导体区域的一部分上的所述栅绝缘膜，所述栅极绝缘膜位于所述第一铁磁层叠膜和所述第二铁磁性堆叠膜之间; 以及形成在栅极绝缘膜上的栅极。
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56.发明授权公开(公告)号：US08335059B2
公开(公告)日：2012-12-18
申请号：US13533198
申请日：2012-06-26
CPC分类号： G11B5/3909 , B82Y10/00 , B82Y25/00 , G01R33/098 , G11B5/3906 , G11C11/161 , G11C11/1659 , H01F10/1936 , H01F10/3254 , H01F10/3295 , H01L27/228 , H01L29/66984 , H01L43/08 , H01L43/10
摘要： A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer.
摘要翻译： 磁阻效应元件包括第一铁磁层，Cr层，Heusler合金层，阻挡层和第二铁磁层。 第一铁磁层具有体心立方晶格结构。 Cr层形成在第一铁磁层上并具有体心立方晶格结构。 Heusler合金层形成在Cr层上。 阻挡层形成在Heusler合金层上。 第二铁磁层形成在阻挡层上。
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公开(公告)号：US08330196B2
公开(公告)日：2012-12-11
申请号：US13419947
申请日：2012-03-14
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66984 , H01L21/823814 , H01L21/84 , H01L21/845 , H01L29/41766 , H01L29/456 , H01L29/49 , H01L29/66075
摘要： A semiconductor device according to an embodiment includes: a semiconductor layer; source and drain regions in the semiconductor layer; a magnetic metal semiconductor compound film on each of the source and drain regions, the magnetic metal semiconductor compound film including the same semiconductor as a semiconductor of the semiconductor layer and a magnetic metal; a gate insulating film on the semiconductor layer between the source region and the drain region; a gate electrode on the gate insulating film; a gate sidewall formed at a side portion of the gate electrode, the gate sidewall being made of an insulating material; a film stack formed on the magnetic metal semiconductor compound film on each of the source and drain regions, the film stack including a magnetic layer; and an oxide layer formed on the gate sidewall, the oxide layer containing the same element as an element in the film stack.
摘要翻译： 根据实施例的半导体器件包括：半导体层; 半导体层中的源极和漏极区域; 在源极和漏极区域中的每一个上的磁性金属半导体化合物膜，包括与半导体层的半导体相同的半导体的磁性金属半导体化合物膜和磁性金属; 源极区域和漏极区域之间的半导体层上的栅极绝缘膜; 栅极绝缘膜上的栅电极; 栅极侧壁，其形成在所述栅电极的侧部，所述栅极侧壁由绝缘材料制成; 在所述源极和漏极区域中的每一个上形成在所述磁性金属半导体化合物膜上的膜堆叠，所述膜堆叠包括磁性层; 以及形成在栅极侧壁上的氧化物层，所述氧化物层包含与膜堆叠中的元件相同的元件。
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公开(公告)号：US08243400B2
公开(公告)日：2012-08-14
申请号：US12342383
申请日：2008-12-23
CPC分类号： G11B5/3909 , B82Y10/00 , B82Y25/00 , G01R33/098 , G11B5/3906 , G11C11/161 , G11C11/1659 , H01F10/1936 , H01F10/3254 , H01F10/3295 , H01L27/228 , H01L29/66984 , H01L43/08 , H01L43/10
摘要： A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer.
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公开(公告)号：US08154916B2
公开(公告)日：2012-04-10
申请号：US12889881
申请日：2010-09-24
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： G11C11/14
CPC分类号： G11C14/0081
摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
摘要翻译： 某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接 第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括 连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。
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公开(公告)号：US20120074984A1
公开(公告)日：2012-03-29
申请号：US13238020
申请日：2011-09-21
申请人： Hideyuki SUGIYAMA , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki SUGIYAMA , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： H03K19/177 , H03K5/00
CPC分类号： H03K19/177
摘要： A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.
摘要翻译： 根据实施例的查找表电路包括：可变电阻电路，包括可变电阻器件，并且基于输入信号从可变电阻器件中选择可变电阻器件; 参考电路，其具有可变电阻电路的最大电阻值和最小电阻值之间的电阻值; 第一n沟道MOSFET，其包括连接到可变电阻电路的端子的源极和连接到漏极的栅极; 第二n沟道MOSFET，其包括连接到参考电路的端子的源极和连接到第一n沟道MOSFET的栅极的栅极; 用于向可变电阻电路提供电流的第一电流供应电路; 第二电流供应电路，用于向参考电路提供电流; 以及比较器，用于比较第一输入端和第二输入端的电压。
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