公开(公告)号：US08274551B2

公开(公告)日：2012-09-25

申请号：US12136395

申请日：2008-06-10

Applicant: Yong-tae Kim ,  Jae-seung Kim ,  Seon-deok Hwang

Inventor： Yong-tae Kim ,  Jae-seung Kim ,  Seon-deok Hwang

IPC: H04N15/00 ,  H04N5/92 ,  G06K9/00

CPC classification number: H04N13/189 ,  H04N13/106 ,  H04N13/128 ,  H04N13/161 ,  H04N13/178 ,  H04N13/194 ,  H04N13/282 ,  H04N13/359 ,  H04N19/597 ,  H04N2213/003

Abstract: A method and apparatus for using header information of stereoscopic image data is provided. The method includes using three-dimensional reproduction period information related to three-dimensionally reproduced stereoscopic image data of image data recorded in a payload region of the stereoscopic image bitstream, in a header region of the stereoscopic image bitstream; recording camera information related to cameras used for obtaining a stereoscopic image, in the header region; recording parallax information between base and additional images of the stereoscopic image in the header region; and recording the image data in the payload region of the stereoscopic image bitstream.

Abstract translation: 提供了一种使用立体图像数据的标题信息的方法和装置。 该方法包括使用与立体图像比特流的有效负载区域中记录的图像数据的三维再现的立体图像数据相关的三维再现周期信息，在立体图像比特流的标题区域中; 在头部区域中记录与用于获得立体图像的相机相关的照相机信息; 在标题区域中的立体图像的基础图像和附加图像之间记录视差信息; 并将图像数据记录在立体图像比特流的有效载荷区域中。

公开(公告)号：US08254291B2

公开(公告)日：2012-08-28

申请号：US12638002

申请日：2009-12-15

Applicant: Kye-hyun Ahn ,  Seung-hwan Kim ,  Yong-tae Kim ,  Kyeong-eun Han ,  Kwang-joon Kim

Inventor： Kye-hyun Ahn ,  Seung-hwan Kim ,  Yong-tae Kim ,  Kyeong-eun Han ,  Kwang-joon Kim

IPC: H04L12/28

CPC classification number: H04L25/14

Abstract: An Ethernet device having multiple lanes and a method of operating the lanes are provided. In one general aspect, it is possible to allocate a dummy block to each of one or more lanes such that the lanes do not selectively participate in communications. In addition, on a receiving side, the dummy block can be removed from among the genuine data blocks to enable data to be decoded. In this case, an Ethernet device on a transmission side and an Ethernet device on a receiving side can exchange information of a lane to which the dummy block is allocated by use of a lane status message, and the lane status message may be based on a link fault message specified by Ethernet standards.

Abstract translation: 提供了一种具有多个通道的以太网设备和一个操作车道的方法。 在一个一般方面，可以将一个虚拟块分配给一个或多个车道中的每一个，使得车道不选择性地参与通信。 此外，在接收侧，可以从正版数据块中移除伪块，以使数据被解码。 在这种情况下，发送侧的以太网设备和接收侧的以太网设备可以通过使用车道状态消息来交换分配了虚拟块的通道的信息，并且车道状态消息可以基于 链路故障信息由以太网标准指定。

公开(公告)号：US20100260498A1

公开(公告)日：2010-10-14

申请号：US12747330

申请日：2009-04-28

Applicant: Kwang-ok Kim ,  Yong-tae Kim ,  Dong-soo Lee

Inventor： Kwang-ok Kim ,  Yong-tae Kim ,  Dong-soo Lee

IPC: H04J14/00

CPC classification number: H04J3/1694 ,  H04Q11/0067 ,  H04Q2011/0064

Abstract: A gigabit passive optical network (GPON) system for fiber to the home (FTTH) service must provide a down-stream data rate of an optical band to provide IPTV service with hundreds of channels to subscribers, and must be able to provide an upstream data rate of an optical band using a currently available BM-IC chip. A currently available BM-IC chip for a GPON has 1.244 Gbps and 2.488 Gbps modes. Accordingly, an optical network terminal (ONT) for a GPON that is capable of providing a downstream transmission band of 10-Gbps and an upstream transmission band of 1.244 Gbps or 2.488 Gbps, and a method for processing an upstream frame in the terminal, are provided. The GPON ONT can provide 20 Mbps, high-definition IPTV service with 500 channels and can provide both upstream data rates of 1.244 Gbps and 2.488 Gbps according to a user's selection without using an additional device.

Abstract translation: 用于光纤到家庭（FTTH）业务的千兆无源光网络（GPON）系统必须提供光带的下行数据速率，以向用户提供数百个信道的IPTV服务，并且必须能够提供上行数据 使用当前可用的BM-IC芯片的光学带宽率。 目前用于GPON的BM-IC芯片具有1.244 Gbps和2.488 Gbps模式。 因此，能够提供10Gbps的下行传输频带和1.244Gbps或2.488Gbps的上行传输频带的GPON的光网络终端（ONT）以及用于处理终端中的上行帧的方法是 提供。 GPON ONT可以提供具有500个通道的20 Mbps高清晰度IPTV服务，并可根据用户的选择提供1.244 Gbps和2.488 Gbps的上行数据速率，而无需使用其他设备。

公开(公告)号：US07768061B2

公开(公告)日：2010-08-03

申请号：US11600765

申请日：2006-11-17

Applicant: Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

Inventor： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.

Abstract translation: 自对准1比特氧化硅氮氧化物硅（SONOS）单元及其制造方法在相邻SONOS单元之间具有高均匀性，因为当蚀刻1比特的字线时，氮化物层的长度不会由于未对准而变化 SONOS细胞。 在半导体衬底上形成形成字线侧壁的绝缘层图案，在其侧壁上形成用于栅极的字线。 使用自对准蚀刻间隔物蚀刻ONO层提供均匀的相邻SONOS电池。

公开(公告)号：US07221028B2

公开(公告)日：2007-05-22

申请号：US10899371

申请日：2004-07-26

Applicant: Tae-kwang Yu ,  Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

Inventor： Tae-kwang Yu ,  Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

IPC: H01L29/72

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/7835

Abstract: The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.

Abstract translation: 本发明涉及高压晶体管及其制造方法。 高压晶体管包括：形成在半导体衬底中的沟道区; 形成在半导体衬底的沟道区上的栅极绝缘膜; 低浓度源极区和低浓度漏极区，其间具有沟道区，并且各自形成在半导体衬底中; 高浓度源区，其形成为与沟道区隔开第一距离; 高浓度漏区，其形成为与沟道区隔开距离大于第一距离的第二距离; 栅极电极，其具有与沟道区域上的栅极绝缘膜接合的栅极底部，以及与栅极底部一体化并且从栅极底部的顶部突出预定长度的栅极顶部，以在低于 浓度排水区; 形成在高浓度源区上的第一金属硅化物层; 以及形成在高浓度漏极区上的第二金属硅化物层。

公开(公告)号：US20070025368A1

公开(公告)日：2007-02-01

申请号：US10558426

申请日：2004-05-14

Applicant: Sam-Chul Ha ,  Seung-Myan Baek ,  Koon-Seok Lee ,  Yong-tae Kim

Inventor： Sam-Chul Ha ,  Seung-Myan Baek ,  Koon-Seok Lee ,  Yong-tae Kim

IPC: H04L12/56

CPC classification number: H04L43/00 ,  H04L12/2803 ,  H04L12/2818 ,  H04L12/2825 ,  H04L43/0817 ,  H04L2012/2849

Abstract: The present invention discloses a home network system using a living network control protocol. The home network system includes: at least one electric device; first and second networks based on a predetermined living network control protocol (LnCP); an LnCP access device connected to the electric device through the second network; and a network manager connected to the LnCP access device through the first network, for controlling and monitoring the electric device.

Abstract translation: 本发明公开了一种使用生活网络控制协议的家庭网络系统。 家庭网络系统包括：至少一个电子设备; 基于预定的生活网络控制协议（LnCP）的第一和第二网络; 通过第二网络连接到电气设备的LnCP接入设备; 以及通过第一网络连接到LnCP接入设备的网络管理器，用于控制和监视电子设备。

公开(公告)号：US07029974B2

公开(公告)日：2006-04-18

申请号：US11083130

申请日：2005-03-17

Applicant: Heeseog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim ,  Yong-suk Choi

Inventor： Heeseog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim ,  Yong-suk Choi

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881

Abstract: A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask layer pattern is formed on the floating-gate conductive layer to define a first opening extending in a first direction. First sacrificial spacers having a predetermined width are formed on both sidewalls corresponding to the mask layer pattern. An inter-gate insulating layer is formed on the floating-gate conductive layer. The first sacrificial spacers are removed, and the floating-gate conductive layer is etched until the gate insulating layer is exposed. A tunneling insulating layer is formed on an exposed portion of the floating-gate conductive layer. A control-gate conductive layer is formed on a surface of the semiconductor substrate. Second sacrificial spacers having predetermined widths are formed on the control-gate conductive layer. A split control gate is formed in the first opening, by etching the exposed control-gate conductive layer. The remaining mask layer pattern and inter-gate insulating layer are etched until the floating-gate conductive layer is exposed. The exposed floating-gate conductive layer is etched to form a split floating gate in the first opening.

Abstract translation: 提供一种分离栅极型非易失性半导体存储器件及其制造分离栅型非易失性半导体存储器件的方法。 在半导体衬底上形成栅绝缘层和浮栅导电层。 掩模层图案形成在浮栅导电层上以限定沿第一方向延伸的第一开口。 具有预定宽度的第一牺牲间隔物形成在对应于掩模层图案的两个侧壁上。 栅极间绝缘层形成在浮栅导电层上。 去除第一牺牲间隔物，并且蚀刻浮栅导电层，直到露出栅极绝缘层。 隧道绝缘层形成在浮栅导电层的露出部分上。 在半导体衬底的表面上形成控制栅导电层。 在控制栅极导电层上形成具有预定宽度的第二牺牲间隔物。 通过蚀刻暴露的控制栅极导电层，在第一开口中形成分裂控制栅极。 蚀刻剩余的掩模层图案和栅极间绝缘层，直到浮栅导电层露出。 蚀刻暴露的浮栅导电层，以在第一开口中形成分离浮栅。

公开(公告)号：US20050029574A1

公开(公告)日：2005-02-10

申请号：US10912046

申请日：2004-08-06

Applicant: Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

Inventor： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.

Abstract translation: 自对准1比特氧化硅氮氧化物硅（SONOS）单元及其制造方法在相邻SONOS单元之间具有高均匀性，因为当蚀刻1比特的字线时，氮化物层的长度不会由于未对准而变化 SONOS细胞。 在半导体衬底上形成形成字线侧壁的绝缘层图案，在其侧壁上形成用于栅极的字线。 使用自对准蚀刻间隔物蚀刻ONO层提供均匀的相邻SONOS电池。