公开(公告)号：US10341230B2

公开(公告)日：2019-07-02

申请号：US15626644

申请日：2017-06-19

Applicant: INTEL CORPORATION

Inventor： Eliezer Tamir ,  Ben-Zion Friedman

IPC: H04L12/721 ,  H04L12/805

Abstract: Examples are disclosed for forwarding or receiving data segments associated with a large data packets. In some examples, a large data packet may be segmented into a number of data segments having separate headers that include identifiers to associate the data segments with the large data packet. The data segments with separate headers may then be forwarded from a network node via a communication channel. In other examples, the data segments with separate headers may be received at another network node and then recombined to form the large data packet at the other network node. Other examples are described and claimed.

公开(公告)号：US10275558B2

公开(公告)日：2019-04-30

申请号：US15344923

申请日：2016-11-07

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Ben-Zion Friedman ,  Alexey Puzhevich ,  Shai Krigman

IPC: G06F17/50 ,  G06F13/16 ,  G06F13/28

Abstract: Technologies for providing FPGA infrastructure-as-a-service include a computing device having an FPGA, scheduler logic, and design loader logic. The scheduler logic selects an FPGA application for execution and the design loader logic loads a design image into the FPGA. The scheduler logic receives a ready signal from the FGPA in response to loading the design and sends a start signal to the FPGA application. The FPGA executes the FPGA application in response to sending the start signal. The scheduler logic may time-share the FPGA among multiple FPGA applications. The computing device may include signaling logic to manage signals between a user process and the FPGA application and DMA logic to manage bulk data transfer between the user process and the FPGA application. The computing device may include a user process linked to an FGPA library executed by a processor of the computing device. Other embodiments are described and claimed.

公开(公告)号：US20190050270A1

公开(公告)日：2019-02-14

申请号：US16007330

申请日：2018-06-13

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Eliel Louzoun ,  Ben-Zion Friedman

IPC: G06F9/50 ,  G06F9/455

Abstract: Disclosed herein are systems, devices, and methods for simultaneous multithreading (SMT) with context associations. For example, in some embodiments, a computing device may include: one or more physical cores; and SMT logic to manage multiple logical cores per physical core such that operations of a first computing context are to be executed by a first logical core associated with the first computing context and operations of a second computing context are to be executed by a second logical core associated with the second computing context, wherein the first logical core and the second logical core share a common physical core.

公开(公告)号：US20180173674A1

公开(公告)日：2018-06-21

申请号：US15386833

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Ben-Zion Friedman

IPC: G06F15/80

Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

公开(公告)号：US09986028B2

公开(公告)日：2018-05-29

申请号：US13937014

申请日：2013-07-08

Applicant: Intel Corporation

Inventor： Phil C. Cayton ,  Eliezer Tamir ,  Frank L. Berry ,  Donald E. Wood

IPC: G06F15/167 ,  H04L29/08

CPC classification number: H04L67/1095 ,  H04L67/1097

Abstract: Examples are disclosed for replicating data between storage servers. In some examples, a network input/output (I/O) device coupled to either a client device or to a storage server may exchange remote direct memory access (RDMA) commands or RDMA completion commands associated with replicating data received from the client device. The data may be replicated to a plurality of storage servers interconnect to each other and/or the client device via respective network communication links. Other examples are described and claimed.

公开(公告)号：US20170155717A1

公开(公告)日：2017-06-01

申请号：US14953750

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Patrick Connor

IPC: H04L29/08 ,  H04L12/741

CPC classification number: H04L67/1097 ,  H04L45/745 ,  H04L69/12

Abstract: Embodiments of the disclosure are directed to controlling an endpoint device running an endpoint device using a central control server. The central controller server is configured to communicate with the endpoint device across a communications interface compliant with a remote direct access (RDMA) compliant protocol. The central control server includes an RDMA network interface controller and a control process. The control process can execute an endpoint device algorithm to identify read and write commands to be sent across the RDMA protocol-compliant interface to the endpoint device. The RDMA network interface controller can convert messages into RDMA compliant messages that include direct read or write commands and memory location information. The endpoint device can also include a network interface controller that can understand the RDMA message, identify the memory location from the message, and execute the direct read or write access command.

公开(公告)号：US09577791B2

公开(公告)日：2017-02-21

申请号：US13705491

申请日：2012-12-05

Applicant: Intel Corporation

Inventor： Eliel Louzoun ,  Radia Perlman ,  Ben-Zion Friedman ,  Ygdal Naouri ,  Eliezer Tamir

IPC: H04L12/28 ,  H04L1/16 ,  H04L1/18 ,  H04L1/00

CPC classification number: H04L1/1657 ,  H04L1/188 ,  H04L2001/0092

Abstract: Methods and apparatus for implementing notification by network elements of packet drops. In response to determining a packet is to be dropped, a network element such as a switch or router determines the source of the packet and returns a dropped packet notification message to the source. Upon receipt of notification, networking software or embedded hardware on the source causes the dropped packet to be retransmitted. The notification may also be sent from the network element to the destination computer to inform networking software or embedded logic implemented by the destination computer that the packet was dropped and notification to the source has been sent, thus alleviating the destination from needing to send a Selective ACKnowledge (SACK) message to inform the source the packet was not delivered. (Too narrow)

Abstract translation: 用于通过分组丢弃的网元实现通知的方法和装置。 响应于确定要丢弃分组，诸如交换机或路由器的网络元件确定分组的源，并将丢弃的分组通知消息返回给源。 收到通知后，源上的网络软件或嵌入式硬件会导致丢弃的数据包被重新发送。 该通知还可以从网络元件发送到目的地计算机，以通知目的地计算机实现的网络软件或嵌入式逻辑，该分组被丢弃并且向源的通知已经被发送，从而减轻目的地需要发送选择性 确认（SACK）消息以通知源未传送数据包。 （太窄）

公开(公告)号：US20160277425A1

公开(公告)日：2016-09-22

申请号：US14661311

申请日：2015-03-18

Applicant: Intel Corporation

Inventor： Iosif Gasparakis ,  Scott P. Dubal ,  Patrick Connor ,  Kapil Sood ,  Eliezer Tamir

IPC: H04L29/06 ,  H04L9/32

CPC classification number: H04L63/1416 ,  G06F21/60 ,  G06F21/85 ,  G06F2213/3808 ,  H04L9/32 ,  H04L63/0428

Abstract: Network interface devices with remote storage control. In some embodiments, a network interface device may include receiver circuitry and remote storage device control circuitry. The remote storage device control circuitry may be coupled to the receiver circuitry and may share a physical support with the receiver circuitry. The remote storage device control circuitry may be configured to control writing of data from the receiver circuitry to a remote storage device that does not share a physical support with the remote storage device control circuitry.

Abstract translation: 具有远程存储控制的网络接口设备。 在一些实施例中，网络接口设备可以包括接收器电路和远程存储设备控制电路。 远程存储设备控制电路可以耦合到接收器电路，并且可以与接收器电路共享物理支持。 远程存储设备控制电路可以被配置为控制从接收器电路向与远程存储设备控制电路不共享物理支持的远程存储设备的数据写入。

公开(公告)号：US20150234776A1

公开(公告)日：2015-08-20

申请号：US14638756

申请日：2015-03-04

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Ben-Zion Friedman ,  Theodore L. Willke ,  Eliel Louzoun ,  Matthew R. Wilcox ,  Donald E. Wood ,  Steven B. McGowan ,  Robert O. Sharp

IPC: G06F15/173 ,  H04L29/08

CPC classification number: G06F15/17331 ,  G06F13/385 ,  G06F15/167 ,  H04L67/1097

Abstract: An embodiment may include circuitry to facilitate, at least in part, a first network interface controller (NIC) in a client to be capable of accessing, via a second NIC in a server that is remote from the client and in a manner that is independent of an operating system environment in the server, at least one command interface of another controller of the server. The command interface may include at least one controller command queue. Such accessing may include writing at least one queue element to the at least one command queue to command the another controller to perform at least one operation associated with the another controller. The another controller may perform the at least one operation in response, at least in part, to the at least one queue element. Many alternatives, variations, and modifications are possible.

Abstract translation: 一个实施例可以包括至少部分地促进客户端中的第一网络接口控制器（NIC）的电路，以便能够通过远离客户端的服务器中的第二NIC以独立的方式访问 的服务器中的操作系统环境，服务器的另一个控制器的至少一个命令接口。 命令接口可以包括至少一个控制器命令队列。 这种访问可以包括将至少一个队列元素写入至少一个命令队列以命令另一控制器执行与另一个控制器相关联的至少一个操作。 另一个控制器可以至少部分地响应于至少一个队列元素来执行至少一个操作。 许多替代方案，变化和修改是可能的。

公开(公告)号：US11847008B2

公开(公告)日：2023-12-19

申请号：US15951391

申请日：2018-04-12

Applicant: Intel Corporation

Inventor： David Hunt ,  Niall Power ,  Kevin Devey ,  Changzheng Wei ,  Bruce Richardson ,  Eliezer Tamir ,  Andrew Cunningham ,  Chris MacNamara ,  Nemanja Marjanovic ,  Rory Sexton ,  John Browne

IPC: G06F1/00 ,  G06F1/3228 ,  G06F1/3296 ,  G06F15/00 ,  G06F1/324

CPC classification number: G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  G06F15/00

Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.