Construction of printed circuit board having a buried via

    公开(公告)号:US10172244B1

    公开(公告)日:2019-01-01

    申请号:US15975726

    申请日:2018-05-09

    Abstract: Method of constructing a printed circuit board, preferably with one lamination step: constructing multilayer cores wherein each multilayer core includes a sheet of cured dielectric material having a layer of metal on each side of the sheet of cured dielectric material; patterning each layer of metal to form wiring traces; forming a sheet of uncured dielectric material; embedding a solder element in the sheet of the uncured dielectric material; alternately stacking the multilayer cores with the sheets of uncured dielectric material, the sheet of the uncured dielectric material having the embedded solder element positioned so as to be aligned with wiring traces in adjacent layers of metal in adjacent multilayer cores; heating the solder element so as to cause the solder element to melt; and hot pressing the stack of multilayer cores and sheets of uncured dielectric material to cause curing of the sheets of uncured dielectric material.

    CABLE CASSETTE APPARATUS
    52.
    发明申请

    公开(公告)号:US20180224908A1

    公开(公告)日:2018-08-09

    申请号:US15945881

    申请日:2018-04-05

    CPC classification number: G06F1/183

    Abstract: An apparatus includes a cassette. The cassette includes a carriage. The carriage is retained internally to the cassette. The apparatus further includes a booklet assembly. The booklet assembly includes a cable connector. The cable connector is affixed internally to the booklet assembly. The cassette is configured for insertion into the booklet assembly. The apparatus further includes a cable assembly. The cable assembly is configured for insertion into the cable connector. The carriage is configured for retaining the cable assembly. In an aspect, a method of using the apparatus includes preloading the cable assembly into the carriage, inserting the cassette into the booklet assembly, and configuring the carriage such that the cable assembly is inserted into the cable connector and retained in an inserted position by the carriage.

    CABLE CASSETTE APPARATUS
    53.
    发明申请

    公开(公告)号:US20180224907A1

    公开(公告)日:2018-08-09

    申请号:US15945869

    申请日:2018-04-05

    CPC classification number: G06F1/183

    Abstract: An apparatus includes a cassette. The cassette includes a carriage. The carriage is retained internally to the cassette. The apparatus further includes a booklet assembly. The booklet assembly includes a cable connector. The cable connector is affixed internally to the booklet assembly. The cassette is configured for insertion into the booklet assembly. The apparatus further includes a cable assembly. The cable assembly is configured for insertion into the cable connector. The carriage is configured for retaining the cable assembly. In an aspect, a method of using the apparatus includes preloading the cable assembly into the carriage, inserting the cassette into the booklet assembly, and configuring the carriage such that the cable assembly is inserted into the cable connector and retained in an inserted position by the carriage.

    REMOVABLE TRANSIENT VOLTAGE DETECTOR
    55.
    发明申请

    公开(公告)号:US20180088157A1

    公开(公告)日:2018-03-29

    申请号:US15275532

    申请日:2016-09-26

    CPC classification number: G01R19/16576 G01R1/206 G01R19/0053

    Abstract: An apparatus and method for detecting transient voltage at an electrical component of a circuit board is provided. The apparatus including a circuit including a comparator and a latch, wherein a first input of the comparator is electrically coupled to the electrical component, and the comparator receives a threshold voltage at a second input, where the comparator outputs either a high signal or a low signal in response to both the first input and the second input, and an output of the comparator is electrically coupled to an input of the latch such that the latch outputs a high signal in response to receiving a high signal from the comparator, and an indicator electrically coupled to an output of the latch, and where the apparatus is mounted non-permanently to the circuit board to provide a non-permanent electrical coupling between the comparator and the electrical component.

    SIGNAL VIA POSITIONING IN A MULTI-LAYER CIRCUIT BOARD USING A GENETIC VIA PLACEMENT SOLVER

    公开(公告)号:US20180068048A1

    公开(公告)日:2018-03-08

    申请号:US15813233

    申请日:2017-11-15

    Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

    SIGNAL VIA POSITIONING IN A MULTI-LAYER CIRCUIT BOARD

    公开(公告)号:US20180060478A1

    公开(公告)日:2018-03-01

    申请号:US15800151

    申请日:2017-11-01

    CPC classification number: G06F17/5077

    Abstract: One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias and is transmitted over a network to support circuit board manufacturing operations.

    Signal via positioning in a multi-layer circuit board using a genetic via placement solver

    公开(公告)号:US09881115B2

    公开(公告)日:2018-01-30

    申请号:US15139653

    申请日:2016-04-27

    CPC classification number: G06F17/5072 G06F17/5081

    Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

    Signal via positioning in a multi-layer circuit board using a genetic via placement solver

    公开(公告)号:US09875331B2

    公开(公告)日:2018-01-23

    申请号:US15430970

    申请日:2017-02-13

    CPC classification number: G06F17/5072 G06F17/5081

    Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

    CABLE CASSETTE APPARATUS
    60.
    发明申请

    公开(公告)号:US20170269643A1

    公开(公告)日:2017-09-21

    申请号:US15071440

    申请日:2016-03-16

    CPC classification number: G06F1/183

    Abstract: An apparatus includes a cassette. The cassette includes a carriage. The carriage is retained internally to the cassette. The apparatus further includes a booklet assembly. The booklet assembly includes a cable connector. The cable connector is affixed internally to the booklet assembly. The cassette is configured for insertion into the booklet assembly. The apparatus further includes a cable assembly. The cable assembly is configured for insertion into the cable connector. The carriage is configured for retaining the cable assembly. In an aspect, a method of using the apparatus includes preloading the cable assembly into the carriage, inserting the cassette into the booklet assembly, and configuring the carriage such that the cable assembly is inserted into the cable connector and retained in an inserted position by the carriage.

Patent Agency Ranking