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    Signal via positioning in a multi-layer circuit board
    1.
    发明授权
    Signal via positioning in a multi-layer circuit board 有权

    公开(公告)号：US09916410B2

    公开(公告)日：2018-03-13

    申请号：US14745964

    申请日：2015-06-22

    申请人： International Business Machines Corporation

    发明人： Sungjun Chun ,  Matteo Cocchini ,  Michael A. Cracraft

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout that includes via groups in a two-to-one signal-to-ground via ratio configuration. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias.

    SIGNAL VIA POSITIONING IN A MULTI-LAYER CIRCUIT BOARD USING A GENETIC VIA PLACEMENT SOLVER
    2.
    发明申请
    SIGNAL VIA POSITIONING IN A MULTI-LAYER CIRCUIT BOARD USING A GENETIC VIA PLACEMENT SOLVER 有权

    公开(公告)号：US20170316139A1

    公开(公告)日：2017-11-02

    申请号：US15139653

    申请日：2016-04-27

    申请人： International Business Machines Corporation

    发明人： Sungjun Chun ,  Matteo Cocchini ,  Michael A. Cracraft

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5081

    摘要： One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

    Multi-layer circuit substrate fabrication method providing improved transmission line integrity and increased routing density
    7.
    发明授权
    Multi-layer circuit substrate fabrication method providing improved transmission line integrity and increased routing density 有权
    提供改进的传输线完整性和增加路由密度的多层电路基板制造方法

    公开(公告)号：US08962475B2

    公开(公告)日：2015-02-24

    申请号：US14080907

    申请日：2013-11-15

    申请人： International Business Machines Corporation

    发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

    摘要： An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

    摘要翻译： 集成电路衬底被设计和制造，具有选择性地施加的传输线参考平面金属层，以实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输线参考平面金属层之间的电容引起的阻抗下降。 传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级 从信号承载PTH的顶部（或底部）到传输线参考平面。 对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

    System for designing substrates having reference plane voids with strip segments
    8.
    发明授权
    System for designing substrates having reference plane voids with strip segments 有权
    用于设计具有带段的参考平面空隙的基板的系统

    公开(公告)号：US08813000B2

    公开(公告)日：2014-08-19

    申请号：US14042908

    申请日：2013-10-01

    申请人： International Business Machines Corporation

    发明人： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

    摘要： Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

    摘要翻译： 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。