公开(公告)号：US11239236B2

公开(公告)日：2022-02-01

申请号：US16827566

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Ehren Mannebach ,  Patrick Morrow ,  Willy Rachmady

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/10

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.

公开(公告)号：US20210305098A1

公开(公告)日：2021-09-30

申请号：US16832500

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Ehren Mannebach ,  Nafees Kabir ,  Patrick Morrow ,  Gilbert Dewey ,  Willy Rachmady ,  Anh Phan

IPC: H01L21/822 ,  H01L27/088 ,  H01L23/528 ,  H01L29/04 ,  H01L21/768 ,  H01L29/16 ,  H01L21/311 ,  H01L23/522

Abstract: Integrated circuitry comprising stacked first and second transistor structures. One of a source, drain or gate terminal of an upper-level transistor structure is coupled to one of a source, drain or gate terminal of a lower-level transistor structure through an asymmetrical interconnect having a lateral width that increases within a dimension parallel to a semiconductor sidewall of the upper-level transistor by a greater amount than in an orthogonal dimension. A dielectric material between the upper and lower transistor structures may be anisotropically etched asymmetrically by orienting a workpiece to be non-orthogonal to a reactive ion flux. Varying an angle between the reactive ion flux and a plane of the second transistor during an etch of the dielectric material may ensure an etched opening is of sufficient bottom dimension to expose a terminal of the lower-level transistor even if not perfectly aligned with the second transistor structure.

公开(公告)号：US20200098756A1

公开(公告)日：2020-03-26

申请号：US16138356

申请日：2018-09-21

Applicant: INTEL CORPORATION

Inventor： Aaron Lilak ,  Stephen Cea ,  Gilbert Dewey ,  Willy Rachmady ,  Roza Kotlyar ,  Rishabh Mehandru ,  Sean Ma ,  Ehren Mannebach ,  Anh Phan ,  Cheng-Ying Huang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8238

Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.