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    Cache management
    51.
    发明授权
    Cache management 有权

    公开(公告)号：US11010307B2

    公开(公告)日：2021-05-18

    申请号：US16699883

    申请日：2019-12-02

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Deanna P. D. Berger ,  Christian Jacobi ,  Martin Recktenwald ,  Yossi Shapira ,  Aaron Tsai

    IPC分类号： G06F12/123 ,  G06F12/0817 ,  G06F12/0811 ,  G06F12/02 ,  G06F12/084

    摘要： A method, a computer system, and a computer program product to perform a directory lookup in a first level cache for requested cache line data. A first processor core can detect that the requested cache line data is not found in a plurality of sets of data in the first level cache and detect that existing cache line data stored in a least recently used data set stored in the first level cache is in an exclusive state, wherein the existing cache line data stored in the least recently used data set is to be overwritten by the requested cache line data retrieved from a second level cache. Furthermore, the first processor core can send a request for the requested cache line data and a physical address of the least recently used data set to the second level cache and execute additional instructions based on the first level cache and data retrieved from the second level cache.

    Efficient pointer load and format
    55.
    发明授权
    Efficient pointer load and format 有权

    公开(公告)号：US10169041B1

    公开(公告)日：2019-01-01

    申请号：US15848353

    申请日：2017-12-20

    申请人： International Business Machines Corporation

    发明人： Eyal Naor ,  Martin Recktenwald ,  Christian Zoellin ,  Aaron Tsai

    IPC分类号： G06F9/30 ,  G06F9/22

    摘要： Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.

    Target buffer address region tracking
    58.
    发明授权
    Target buffer address region tracking 有权
    目标缓冲区地址区域跟踪

    公开(公告)号：US08898427B2

    公开(公告)日：2014-11-25

    申请号：US14088555

    申请日：2013-11-25

    申请人： International Business Machines Corporation

    发明人： James J. Bonanno ,  Brian R. Prasky ,  Aaron Tsai

    IPC分类号： G06F12/02 ,  G06F9/38

    CPC分类号： G06F12/02 ,  G06F9/3806 ,  G11C29/76

    摘要： Embodiments relate to target buffer address region tracking. An aspect includes receiving a restart address, and comparing, by a processing circuit, the restart address to a first stored address and to a second stored address. The processing circuit determines which of the first and second stored addresses is identified as a same range and a different range to form a predicted target address range defining an address region associated with an entry in the target buffer. Based on determining that the restart address matches the first stored address, the first stored address is identified as the same range and the second stored address is identified as the different range. Based on determining that the restart address matches the second stored address, the first stored address is identified as the different range and the second stored address is identified as the same range.

    摘要翻译： 实施例涉及目标缓冲器地址区域跟踪。 一个方面包括接收重启地址，并且由处理电路将重启地址与第一存储地址和第二存储地址进行比较。 处理电路确定将第一和第二存储的地址中的哪一个识别为相同的范围和不同的范围，以形成定义与目标缓冲器中的条目相关联的地址区域的预测目标地址范围。 基于确定重启地址与第一存储地址匹配，第一存储地址被标识为相同的范围，并且将第二存储地址识别为不同的范围。 基于确定重新启动地址与第二存储地址匹配，将第一存储地址识别为不同的范围，并将第二存储地址识别为相同的范围。

    STORE DATA FORWARDING WITH NO MEMORY MODEL RESTRICTIONS
    59.
    发明申请
    STORE DATA FORWARDING WITH NO MEMORY MODEL RESTRICTIONS 有权
    存储数据转发，无内存模式限制

    公开(公告)号：US20140108743A1

    公开(公告)日：2014-04-17

    申请号：US14059673

    申请日：2013-10-22

    申请人： International Business Machines Corporation

    发明人： Brian D. Barrick ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  Aaron Tsai ,  Chung-Lung K. Shum ,  Michael H. Wood

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0855 ,  G06F9/3826 ,  G06F9/3834

    摘要： Embodiments relate to loading data in a pipelined microprocessor. An aspect includes issuing a load request that comprises a load address requiring at least one block of data the same size as a largest contiguous granularity of data returned from a cache. Another aspect includes determining that the load address matches at least one block address. Another aspect includes, based on determining that there is an address match, reading a data block from a buffer register and sending the data to satisfy the load request; comparing a unique set id of the data block to the set id of the matching address after sending the data block; based on determining that there is a set id match, continuing the load request, or, based on determining that there is not a set id match, setting a store-forwarding state of the matching address to no store-forwarding and rejecting the load request.

    摘要翻译： 实施例涉及在流水线微处理器中加载数据。 一方面包括发布加载请求，该加载请求包括需要至少一个与高速缓存返回的最大连续粒度数据相同大小的数据块的加载地址。 另一方面包括确定加载地址与至少一个块地址匹配。 另一方面包括：基于确定存在地址匹配，从缓冲寄存器读取数据块并发送数据以满足加载请求; 在发送数据块之后，将数据块的唯一集合ID与匹配地址的集合ID进行比较; 基于确定存在设置id匹配，继续加载请求，或者基于确定没有设置id匹配，将匹配地址的存储转发状态设置为不存储转发并拒绝加载请求 。