公开(公告)号：US09947795B2

公开(公告)日：2018-04-17

申请号：US15388720

申请日：2016-12-22

Applicant: Japan Display Inc.

Inventor： Hajime Watakabe ,  Tomoyuki Ariyoshi ,  Akihiro Hanada

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/24 ,  H01L27/12 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L29/78606 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869

Abstract: According to one embodiment, a thin-film transistor includes a first insulating film, an oxide semiconductor layer provided on the first insulating film and a second insulating film provided on the oxide semiconductor layer, and at least one of the first insulating film and the second insulating film includes a first region in contact with the oxide semiconductor layer and a second region further distant from the oxide semiconductor layer than the first region, and the second region has an argon concentration higher than that of the first region.

公开(公告)号：US09780227B2

公开(公告)日：2017-10-03

申请号：US14944676

申请日：2015-11-18

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Masayoshi Fuchi ,  Hajime Watakabe ,  Takashi Okada ,  Arichika Ishida

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/467

CPC classification number: H01L29/7869 ,  H01L21/467 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78696

Abstract: According to one embodiment, a thin-film transistor and a method of manufacturing the thin-film transistor provided herein achieve enhanced reliability by preventing a disconnection in a gate insulating film at a position corresponding to an end surface of an oxide semiconductor layer. The oxide semiconductor layer includes a channel region, a source region, and a drain region. The channel region is placed between the source region and the drain region. The gate insulating film covers the oxide semiconductor layer in a range from at least a part of an upper surface to an end surface continuous with the upper surface of the oxide semiconductor layer. The oxide semiconductor layer is formed so as to have an oxygen concentration that becomes lower from a top side to a bottom side and the end surface is inclined so as to diverge from the top side to the bottom side.

公开(公告)号：US09123588B2

公开(公告)日：2015-09-01

申请号：US14206858

申请日：2014-03-12

Applicant: JAPAN DISPLAY INC.

Inventor： Tetsuya Shibata ,  Hajime Watakabe ,  Atsushi Sasaki ,  Yuki Matsuura ,  Muneharu Akiyoshi ,  Hiroyuki Watanabe

IPC: H01L29/72 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1225 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: According to one embodiment, a method of manufacturing a thin-film transistor circuit substrate including forming an oxide semiconductor thin film above an insulative substrate, forming a gate insulation film and a gate electrode which are stacked on a first region of the oxide semiconductor thin film, and exposing from the gate insulation film a second region and a third region of the oxide semiconductor thin film, the second region and the third region being located on both sides of the first region of the oxide semiconductor thin film, forming an interlayer insulation film of silicon nitride including dangling bonds of silicon, the interlayer insulation film covering the second region and the third region of the oxide semiconductor thin film, the gate insulation film and the gate electrode, and forming a source electrode and a drain electrode.

Abstract translation: 根据一个实施例，制造薄膜晶体管电路衬底的方法包括在绝缘衬底上形成氧化物半导体薄膜，形成栅极绝缘膜和栅电极，所述栅极绝缘膜和栅电极层叠在氧化物半导体薄膜的第一区域上 并且从所述栅极绝缘膜暴露所述氧化物半导体薄膜的第二区域和第三区域，所述第二区域和所述第三区域位于所述氧化物半导体薄膜的所述第一区域的两侧，形成层间绝缘膜 包括硅的悬挂键，覆盖第二区域的层间绝缘膜和氧化物半导体薄膜的第三区域，栅极绝缘膜和栅电极，以及形成源电极和漏电极。